GD25Q128ESIGR

The GD25Q128E (128M-bit) Serial flash supports the standard Serial Peripheral Interface (SPI), and the Dual/Quad SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (WP#), I/O3 (HOLD#/RESET#). The Dual I/O data is transferred with speed of 266Mbit/s, and the Quad I/O data is transferred with speed of 532Mbit/s.

Key features

• 128M-bit Serial Flash
• 16M-Byte
• 256 Bytes per programmable page
• Standard, Dual, Quad SPI
• Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD#, RESET#
• Dual SPI: SCLK, CS#, IO0, IO1, WP#, HOLD#, RESET#
• Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3, RESET#
• Fast Program/Erase Speed
• Page Program time: 0.5ms typical
• Sector Erase time: 45ms typical
• Block Erase time: 0.15s/0.25s typical
• Chip Erase time: 50s typical
• Flexible Architecture
• Uniform Sector of 4K-Byte
• Uniform Block of 32/64K-Byte
• High Speed Clock Frequency
• 133MHz for fast read with 30PF load
• Dual I/O Data transfer up to 266Mbits/s
• Quad I/O Data transfer up to 532Mbits/s
• Low Power Consumption
• 14μA typical standby current
• 1μA typical deep power down current
• Software/Hardware Write Protection
• Write protect all/portion of memory via software
• Enable/Disable protection with WP# Pin
• Top/Bottom Block protection
• Advanced Security Features
• 128-bit Unique ID for each device
• Serial Flash Discoverable parameters (SFDP) register
• 3x1024-Byte Security Registers With OTP Locks
• Endurance and Data Retention
• Minimum 100,000 Program/Erase Cycles
• 20-year data retention typical
• Allows XiP (eXecute in Place) Operation
• High speed Read reduce overall XiP instruction fetch time
• Continuous Read with Wrap further reduce data latency to fill up SoC cache
• Single Power Supply Voltage
• Full voltage range: 2.7-3.6V
• Package Information
• SOP8 208mil
• SOP16 300mil
• USON8 (4x4mm, 0.45mm thickness)
• WSON8 (6x5mm)
• WSON8 (8x6mm)
• TFBGA-24ball (6x4 Ball Array)
• TFBGA-24ball (5x5 Ball Array)