H5AN8G6NDJR-XNC

H5AN8G4NDJR-xxC, H5AN8G8NDJR-xxC, H5AN8G6NDJR-xxC are 8Gb CMOS Double Data Rate IV (DDR4) Synchronous Dynamic Random Access Memory devices, ideally suited for main memory applications requiring high storage density and high bandwidth. The 8Gb DDR4 SDRAM provides fully synchronous operation referenced to both rising and falling edges of the clock. All address and control inputs are latched on the rising edge of CK (falling edge of CK), while data, data strobe, and write data mask inputs are sampled on both rising and falling edges of the clock. The data path features an internal pipeline architecture with 8-bit prefetch to achieve extremely high bandwidth.

Key features

• Operating voltage VDD = VDDQ = 1.2V ± 0.06V
• Fully differential clock input (CK, CK̄) operation
• Differential data strobe (DQS, DQS̄)
• On-die DLL aligns DQ, DQS, and DQS̄ transitions to CK transitions
• Data mask blocks write data at both rising and falling edges of the data strobe
• All address and control inputs, except data, data strobe, and data mask, are latched on the rising edge of the clock
• Programmable CAS latency supported: 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, and 20
• Programmable additive latency supported: 0, CL-1, and CL-2 (x4/x8 only)
• Programmable CAS write latency (CWL) = 9, 10, 11, 12, 14, 16, 18
• Programmable burst length 4/8 with nibble sequential and interleave modes
• Burst length on-the-fly switching supported
• 16 banks
• Average refresh interval (case temperature 0°C ~ 95°C)
• 7.8 μs at 0°C ~ 85°C
• 3.9 μs at 85°C ~ 95°C
• JEDEC-compliant 78-ball FBGA package (x4/x8) and 78-ball FBGA package (x16)
• Drive strength selection via mode register
• Dynamic on-die termination supported
• Two termination states supported (e.g., RTT_PARK and RTT_NOM), switchable via ODT pin
• Asynchronous reset pin supported
• ZQ calibration supported
• TDQS (Termination Data Strobe, x8 only) supported
• Write leveling supported
• 8-bit prefetch
• RoHS compliant
• Internal Vref DQ level generation supported
• Write CRC supported for all speed grades
• Maximum power saving mode supported
• Temperature-controlled auto-refresh mode supported
• Low-power auto self-refresh mode supported
• Fine granularity refresh supported
• Per-DRAM addressability supported
• Gear-down mode (1/2 rate, 1/4 rate) supported
• Programmable read/write preamble supported
• Self-refresh abort supported
• Command/address parity mode supported
• Bank grouping with CAS-to-CAS latency for accesses to banks in the same or different bank groups
• Data bus inversion supported (x8 only)