H5TQ4G63EFR-RDC

The H5TQ4G83EFR-xxC, H5TQ4G63EFR-xxC, H5TQ4G83EFR-xxI, H5TQ4G63EFR-xxI, H5TQ4G83EFR-xxL, H5TQ4G63EFR-xxL, H5TQ4G83EFR-xxJ, H5TQ4G63EFR-xxJ, H5TQ4G83EFR-xxK and H5TQ4G63EFR-xxK are a 4,294,967,296-bit CMOS Double Data Rate III (DDR3) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. 4Gb DDR3 SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth.

Key features

• VDD = VDDQ = 1.5V + 1 - 0.075V
• Fully differential clock inputs (CK, CK) operation
• Differential Data Strobe (DQS, DQS)
• On chip DLL align DQ, DQS and DQS transition with CK transition
• DM masks write data-in at the both rising and falling edges of the data strobe
• All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock
• Programmable CAS latency 5, 6, 7, 8, 9, 10, 11, 13 and 14 supported
• Programmable additive latency 0, CL - 1, and CL - 2 supported
• Programmable CAS Write latency (CWL) = 5, 6, 7, 8, 9 and 10
• Programmable burst length 4/8 with both nibble sequential and interleave mode
• BL switch on the fly
• 8 banks
• Average Refresh Cycle:
• Tcase of 0 ℃ ∼ 95 ℃: 7.8 μs at 0 ℃ ∼ 85 ℃; 3.9 μs at 85 ℃ ∼ 95 ℃; 1.95 μs at 85 ℃ ∼ 95 ℃
• Commercial Temperature (0 ℃ ∼ 95 ℃)
• Industrial Temperature (-40 ℃ ∼ 95 ℃)
• Automotive Temperature (-40 ℃ ∼ 105 ℃)
• JEDEC standard 78 ball FBGA(x8), 96 ball FBGA (x16)
• Driver strength selected by EMRS
• Dynamic On Die Termination supported
• Asynchronous RESET pin supported
• ZQ calibration supported
• TDQS (Termination Data Strobe) supported (x8 only)
• Write Levelization supported
• 8 bit pre - fetch