IS25LP032D-JBLE-TR

The IS25LP032D and IS25WP032D Serial Flash memory offers a versatile storage solution with high flexibility and performance in a simplified pin count package. The device is accessed through a 4-wire SPI Interface consisting of a Serial Data Input (SI), Serial Data Output (SO), Serial Clock (SCK), and Chip Enable (CE#) pins, which can also be configured to serve as multi-I/O. The device supports Dual and Quad I/O as well as standard, Dual Output, and Quad Output SPI. Clock frequencies of up to 133MHz allow for equivalent clock rates of up to 532MHz (133MHz x 4) which equates to 66Mbytes/s of data throughput. The IS25xP series of Flash adds support for DTR (Double Transfer Rate) commands that transfer addresses and read data on both edges of the clock. These transfer rates can outperform 16-bit Parallel Flash memories allowing for efficient memory access to support XIP (execute in place) operation. Initial state of the memory array is erased (all bits are set to 1) when shipped from the factory. QPI (Quad Peripheral Interface) supports 2-cycle instruction further reducing instruction times. Pages can be erased in groups of 4Kbyte sectors, 32Kbyte blocks, 64Kbyte blocks, and/or the entire chip. The uniform sector and block architecture allows for a high degree of flexibility so that the device can be utilized for a broad variety of applications requiring solid data retention.

Key features

• Industry Standard Serial Interface
• IS25LP032D: 32Mbit/4Mbyte - IS25WP032D: 32Mbit/4Mbyte
• 256 bytes per Programmable Page
• Supports standard SPI, Fast, Dual, Dual I/O, Quad, Quad I/O, SPI DTR, Dual I/O DTR, Quad I/O DTR, and QPI
• Supports Serial Flash Discoverable Parameters (SFDP)
• High Performance Serial Flash (SPI)
• 50MHz Normal and 133Mhz Fast Read
• 532 MHz equivalent QPI
• DTR (Dual Transfer Rate) up to 66MHz
• Selectable Dummy Cycles
• Configurable Drive Strength
• Supports SPI Modes 0 and 3
• More than 100,000 Erase/Program Cycles
• More than 20-year Data Retention
• Flexible & Efficient Memory Architecture
• Chip Erase with Uniform: Sector/Block Erase (4/32/64 Kbyte)
• Program 1 to 256 Bytes per Page
• Program/Erase Suspend & Resume
• Efficient Read and Program modes
• Low Instruction Overhead Operations
• Continuous Read 8/16/32/64-Byte Burst Wrap
• Selectable Burst Length
• QPI for Reduced Instruction Overhead
• AutoBoot Operation
• Low Power with Wide Temp. Ranges
• Single Voltage Supply IS25LP: 2.30V to 3.60V IS25WP: 1.65V to 1.95V
• 4 mA Active Read Current (typ.)
• 10 μA Standby Current (typ.)
• 1 μA Deep Power Down (typ.)
• Temp Grades: Extended: -40℃ to +105℃ Auto Grade (A3): -40℃ to +125℃
• Advanced Security Protection
• Software and Hardware Write Protection
• Power Supply Lock Protect
• 4x256-Byte Dedicated Security Area with OTP User-lockable Bits
• 128 bit Unique ID for Each Device (Call Factory)
• Industry Standard Pin-out & Packages
• B = 8 -pin SOIC 208mil
• N = 8 -pin SOIC 150mil
• T = 8 -contact USON 4x3mm
• E = 8 -contact XSON 4x4mm
• K = 8 -contact WSON 6x5mm
• L = 8 -contact WSON 8x6mm(Call Factory)
• M = 16 -pin SOIC 300mil
• ⊙ = 24 -ball TFBGA 4x6 ARRAY
• H = 24 -ball TFBGA 5x5 ARRAY
• KGD (Call Factory)