MICROCHIP

KSZ8795CLXIC

LQFP-80(10x10) Controllers RoHS

LQFP-80(10x10)ROHS3 CompliantActive

Integrated 5-Port 10/100-Managed Ethernet Switch with Gigabit GMI/RGMII and MII/RMII Interfaces

Manufacturer: MICROCHIP
Manufacturer part #: KSZ8795CLXIC
Store part #: C69416
Package / case: LQFP-80(10x10)
Category: Controllers
Packaging: Tray

Datasheet (PDF)

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2,337 in stock

#C69416

Stock & price checked 6 days ago

Quantity	Unit price	Pack price
1+	₹1,351.97	₹1,351.97
10+	₹1,170.80	₹11,708.00
30+	₹972.44	₹29,173.20
100+	₹879.78	₹87,978.00

Quantity (min 1)

1 × ₹1,351.97

₹1,351.97

excl. GST

₹1,595.32 incl. 18% GST

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Standard pack: 160 per tray

KSZ8795CLXIC

₹1,351.97 for 1 + GST

Specifications

Features: Automatic polarity correction;Low-power mode;Port independent power-down
MAC Address Support: 1024
Number of Channels: 5
MAC Interface: GMII;RGMII;MII;RMII
Voltage - Supply: 3.3V;2.5V;1.8V
Integrated PHY: Yes
Communication Interface: SPI
Operating Temperature: -40℃~+85℃
VLAN Support: 4096
Memory Space: 64KB
Ethernet Speed Standards: 10BASE-T;100BASE-TX;1000BASE-T

Packaging & compliance

RoHS: ROHS3 Compliant
Lifecycle: Active
ECCN: 5A991B1
Packaging: Tray
Standard pack: 160 / Tray
Sold per: Piece
Minimum order: 1
Unit weight: 1.094 g

Overview

Applications

Industrial Ethernet Applications that Employ IEEE 802.3 - Compliant MACs. (Ethernet/IP, Profinet, MODBUS TCP, etc.)
VoIP Phone
Set - Top/Game Box
Automotive
Industrial Control
IPTV POF
SOHO Residential Gateway with Full - Wire Speed of Four LAN Ports
Broadband Gateway/Firewall/VPN
Integrated DSL/Cable Modem
Wireless LAN Access Point + Gateway
Standalone 10/100 Switch
Networked Measurement and Control Systems

Key features

Management Capabilities:
The KSZ8795CLX includes all the functions of a 10/100BASE-T/TX switch system which combines a switch engine, frame buffer management, address look-up table, queue management, MIB counters, media access controllers (MAC), and PHY transceivers.
Non-blocking store-and-forward switch fabric assures fast packet delivery by utilizing a 1024-entries forwarding table.
Port mirroring/monitoring/sniffing: Ingress and/or egress traffic to any port.
MIB counters for fully-compliant statistics gathering (36 counters per port).
Support hardware for port-based flush and freeze command in MIB counter.
Multiple loopback of remote, PHY, and MAC modes support for the diagnostics.
Rapid Spanning Tree Support (RSTP) for topology management and ring/linear recovery.
Robust PHY Ports:
Four integrated IEEE 802.3/802.3u-compliant Ethernet transceivers supporting 10BASE-T and 100BASE-TX.
802.1az EEE supported.
On-chip termination resistors and internal biasing for differential pairs to reduce power.
HP Auto MDI/MDI-X crossover support eliminates the need to differentiate between straight or crossover cables in applications.
MAC and GMAC Ports:
Four internal media access control (MAC1 to MAC4) units and one internal Gigabit media access control (GMAC5) unit.
GMII, RGMII, MII or RMII interfaces support for the Port 5 GMAC5 with uplink.
2 KByte jumbo packet support.
Tail tagging mode (One byte added before FCS) support on Port 5 to inform the processor in which the ingress port receives the packet and its priority.
Supports Reduced Media Independent Interface (RMII) with 50 MHz reference clock output.
Supports Media Independent Interface (MII) in either PHY mode or MAC mode on Port 5.
LinkMD cable diagnostic capabilities for determining cable opens, shorts, and length.
Advanced Switch Capabilities:
Non-blocking store-and-forward switch fabric assures fast packet delivery by utilizing 1024 entry forwarding table.
64 KB frame buffer RAM.
IEEE 802.1q VLAN support for up to 128 active VLAN groups (Full-range 4096 of VLAN IDs).
IEEE 802.1p/Ω tag insertion or removal on a per port basis (Egress).
VLAN ID tag/untag options on per port basis.
Fully compliant with IEEE 802.3/802.3u standards.
IEEE 802.3x full-duplex with force-mode option and half-duplex back-pressure collision flow control.
IEEE 802.1w Rapid Spanning Tree Protocol support.
IGMP v1/v2/v3 snooping for multicast packet filtering.
QoS/CoS packets prioritization support: 802.1p, DiffServ-based and re-mapping of 802.1p priority field per port basis on four priority levels.
IPv4/IPv6 QoS support.
IPV6 Multicast Listener Discovery (MLD) snooping.
Programmable rate limiting at the ingress and egress ports on a per port basis.
Jitter-free per packet based rate limiting support.
Tail tag mode (1 byte added before FCS) support on Port 5 to inform the processor which ingress port receives the packet.
Broadcast storm protection with percentage control (Global and per port basis).
1K entry forwarding table with 64 KB frame buffer.
4 priority queues with dynamic packet mapping for IEEE 802.1P, IPV4 TOS (DIFFSERV), IPv6 traffic class, etc.
Supports WoL using AMD’s Magic Packet.
VLAN and address filtering.
Supports 802.1x port-based security, authentication and MAC-based authentication via Access Control Lists (ACL).
Provides port-based and rule-based ACLs to support Layer 2 MAC SA/DA address, Layer 3 IP address and IP mask, Layer 4 TCP/UDP port number, IP protocol, TCP flag and compensation for the port security filtering.
Ingress and egress rate limit based on bit per second (bps) and packet-based rate limiting (pps).
Configuration Registers Access:
High-speed SPI (4-wire, up to 50 MHz) interface to access all internal registers.
MII Management (MIIM, MDC/MDIO 2-wire) interface to access all PHY registers per Clause 22.2.4.5 of the IEEE 802.3 specification.
I/O pin strapping facility to set certain register bits from I/O pins during reset time.
Control registers configurable on-the-fly.
Power and Power Management:
Full-chip software power-down (All register values are not saved and strap-in value will re-strap after it releases the power-down).
Per-port software power-down.
Energy Detect Power-Down (EDPD), which disables the PHY transceiver when cables are removed.
Supports IEEE P802.3az Energy Efficient Ethernet (EEE) to reduce power consumption in transceivers in LPI state even though cables are not removed.
Dynamic clock tree control to reduce clocking in areas that are not in use.
Low power consumption without extra power consumption on transformers.
Voltages: Using external LDO power supplies.
Analog VDDAT 3.3V or 2.5V.
VDDIO support 3.3V, 2.5V, and 1.8V.
Low 1.2V voltage for analog and digital core power.
WoL support with configurable packet control.
Additional Features:
Single 25 MHz +50 ppm reference clock requirement.
Comprehensive programmable two-LED indicator support for link, activity, full-/halfDuplex, and 10/100 speed.
Packaging and Environmental:
Commercial temperature range: 0°C to +70°C.
Industrial temperature range: -40°C to +85°C.
Package available in an 80-pin LQFP, lead-free (RoHS-compliant) package.
Supports Human Body Model (HBM) ESD rating of 5 kV.
0.065 μm CMOS technology.