LAN9352I/ML

QFN-72-EP(10x10) Controllers RoHS

QFN-72-EP(10x10)ROHS3 CompliantActive

2-Port 10/100 Managed Ethernet Switch with Non-PCI CPU Interface

Manufacturer: MICROCHIP
Manufacturer part #: LAN9352I/ML
Store part #: C633953
Package / case: QFN-72-EP(10x10)
Category: Controllers
Packaging: Tray

Datasheet (PDF)

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Out of stock

#C633953

Stock & price checked 27 h ago

Quantity	Unit price	Pack price
1+	₹1,903.36	₹1,903.36
200+	₹736.55	₹1,47,310.00
500+	₹710.83	₹3,55,415.00
1,000+	₹697.96	₹6,97,960.00

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Standard pack: 168 per tray

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Specifications

MAC Interface: MII
Number of Channels: 2
Features: Support optical fiber;IEEE1588 timestamp;Cable diagnostics;Low-power mode;Power-on reset
Voltage - Supply: 1.8V~3.3V
Ethernet Speed Standards: 10BASE-T;100BASE-TX;100BASE-FX
Data Rate: 10Mbit/s;100Mbit/s

Packaging & compliance

RoHS: ROHS3 Compliant
Lifecycle: Active
ECCN: EAR99
Packaging: Tray
Standard pack: 168 / Tray
Sold per: Piece
Minimum order: 1
Unit weight: 1.486 g

Overview

Applications

Cable, satellite, and IP set-top boxes
Digital televisions & video recorders
VoIP/Video phone systems, home gateways
Test/Measurement equipment, industrial automation

Key features

High performance 2-port switch with VLAN, QoS packet prioritization, rate limiting, IGMP monitoring and management functions
Interfaces to most 8/16-bit embedded controllers and 32-bit embedded controllers with an 8/16-bit bus
Integrated Ethernet PHYs with HP Auto-MDIX
Compliant with Energy Efficient Ethernet 802.3az
Wake on LAN (WoL) support
Integrated IEEE 1588v2 hardware time stamp unit
Cable diagnostic support
1.8V to 3.3V variable voltage I/O
Integrated 1.2V regulator for single 3.3V operation
Ethernet Switch Fabric: 32K buffer RAM, 512 entry forwarding table; Port based IEEE 802.1Q VLAN support (16 groups); Programmable IEEE 802.1Q tag insertion/removal; IEEE 802.1D spanning tree protocol support; 4 separate transmit queues available per port; Fixed or weighted egress priority servicing; QoS/CoS Packet prioritization; Input priority determined by VLAN tag, DA lookup, TOS, DIFFSERV or port default value; Programmable Traffic Class map based on input priority on per port basis; Remapping of 802.1Q priority field on per port basis; Programmable rate limiting at the ingress with coloring and random early discard, per port / priority; Programmable rate limiting at the egress with leaky bucket algorithm, per port / priority; IGMP v1/v2/v3 monitoring for Multicast packet filtering; Programmable broadcast storm protection with global % control and enable per port; Programmable buffer usage limits; Dynamic queues on internal memory; Programmable filter by MAC address
Switch Management: Port mirroring/monitoring/sniffing: ingress and/or egress traffic on any port or port pair; Fully compliant statistics (MIB) gathering counters
2 internal 10/100 PHYs with HP Auto-MDIX support; Fully compliant with IEEE 802.3 standards; 10BASE-T and 100BASE-TX support; 100BASE-FX support via external fiber transceiver; Full and half duplex support, full duplex flow control; Backpressure (forced collision) half duplex flow control; Automatic flow control based on programmable levels; Automatic 32-bit CRC generation and checking; Programmable interframe gap, flow control pause value; Auto-negotiation, polarity correction & MDI/MDI-X
8/16-Bit Host Bus Interface: Indexed register or multiplexed bus; SPI / Quad SPI support
IEEE 1588v2 hardware time stamp unit: Global 64-bit tunable clock; Boundary clock: master / slave, one-step / two-step, end-to-end / peer-to-peer delay; Transparent Clock with Ordinary Clock: master / slave, one-step / two-step, end-to-end / peerto-peer delay; Fully programmable timestamp on TX or RX, timestamp on GPIO; 64-bit timer comparator event generation (GPIO or IRQ)
Comprehensive power management features: 3 power-down levels; Wake on link status change (energy detect); Magic packet wakeup, Wake on LAN (WoL), wake on broadcast, wake on perfect DA; Wakeup indicator event signal
Power and I/O: Integrated power-on reset circuit; Latch-up performance exceeds 150mA per EIA/JESD78, Class II; JEDEC Class 3A ESD performance; Single 3.3V power supply (integrated 1.2V regulator)
Additional Features: Multifunction GPIOs; Ability to use low cost 25MHz crystal for reduced BOM
Packaging: Pb-free RoHS compliant 72-pin QFN or 80-pin TQFPEP
Available in commercial and industrial temp. ranges