
micron
MT40A512M16TB-062E:R
8Gbit 1.6GHz DDR4 SDRAM FBGA-96 Memory
PopularFBGA-96RoHSActive
8Gb DDR4 SDRAM
Datasheet (PDF)
Every Order Guarantee
100% Authentic · 30-Day Return or Replacement · policy
323 in stock
#C2887392
Stock & price checked 33 h ago
| Quantity | Unit price | Pack price |
|---|---|---|
| 1+ | ₹10,786.78 | ₹10,786.78 |
| 10+ | ₹9,845.99 | ₹98,459.90 |
| 30+ | ₹9,504.51 | ₹2,85,135.30 |
| 100+ | ₹8,827.65 | ₹8,82,765.00 |
1 × ₹10,786.78
₹10,786.78
excl. GST
₹12,728.40 incl. 18% GST
- Dispatch in 7–10 working days
- GST invoice with every order
- Standard pack: 2,000 per reel
MT40A512M16TB-062E:R
₹10,786.78 for 1 + GST
Specifications
- Operating Temperature
- 0℃~+95℃
- Features
- Auto self-refresh;Auto precharge function;Write leveling function;CRC function;Dynamic on-chip termination;ZQ calibration function
- Refresh Current
- 8mA
- Memory Size
- 8Gbit
- Voltage - Supply
- 1.14V~1.26V;59mA
- Clock Frequency
- 1.6GHz
- Memory Format
- DDR4 SDRAM
Packaging & compliance
- RoHS
- RoHS
- Lifecycle
- Active
- Moisture sensitivity
- MSL 3 (168 hours)
- ECCN
- 3A991B1A
- Packaging
- Tape & Reel (TR)
- Standard pack
- 2,000 / Reel
- Sold per
- Piece
- Minimum order
- 1
- Unit weight
- 0.669 g
Overview
Key features
- VDD = VDDO = 1.2V ± 60mV,VPP = 2.5V - 125mV + 250mV
- On-die, internal, adjustable VREFDQ generation
- 1.2V pseudo open-drain I/O
- Refresh time of 8192-cycle at TC temperature range: - 64ms at -40℃ to 85℃, - 32ms at >85℃ to 95℃, - 16ms at >95℃ to 105℃
- 16 internal banks (x4, x8): 4 groups of 4 banks each
- 8 internal banks (x16): 2 groups of 4 banks each, 8n-bit prefetch architecture
- Programmable data strobe preambles
- Data strobe preamble training
- Command/Address latency (CAL)
- Multipurpose register READ and WRITE capability
- Write leveling
- Self refresh mode
- Low-power auto self refresh (LPASR)
- Temperature controlled refresh (TCR)
- Fine granularity refresh
- Self refresh abort
- Maximum power saving
- Output driver calibration
- Nominal, park, and dynamic on-die termination (ODT)
- Data bus inversion (DBI) for data bus
- Command/Address (CA) parity
- Databus write cyclic redundancy check (CRC)
- Per-DRAM addressability
- Connectivity test
- JEDEC JESD-79-4 compliant
- sPPR and hPPR capability
- MBIST-PPR support (Die Revision R only)
Alternatives
Similar parts — check the datasheet before substituting.
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