S25FL256SAGNFI000

Key features

• CMOS 3.0 Volt Core with Versatile I/O
• SPI with Multi-I/O
• SPI Clock polarity and phase modes 0 and 3
• DDR option
• Extended Addressing: 24- or 32-bit address options
• Serial Command set and footprint compatible with S25FL-A, S25FL-K, and S25FL-P SPI families
• Multi I/O Command set and footprint compatible with S25FL-P SPI family
• READ Commands
• Normal, Fast, Dual, Quad, Fast DDR, Dual DDR, Quad DDR
• AutoBoot - power up or reset and execute a Normal or Quad read command automatically at a preselected address
• Common Flash Interface (CFI) data for configuration information
• Programming (1.5 MBps)
• 256 or 512 Byte Page Programming buffer options
• Quad-Input Page Programming (QPP) for slow clock systems
• Automatic ECC-internal hardware Error Correction Code generation with single bit error correction
• Erase (0.5 to 0.65 MBps)
• Hybrid sector size option - physical set of thirty two 4-KB sectors at top or bottom of address space with all remaining sectors of 64 KB, for compatibility with prior generation S25-FL devices
• Uniform sector option - always erase 256-KB blocks for software compatibility with higher density and future devices
• Cycling Endurance
• 100,000 Program-Erase Cycles, minimum
• Security features
• OTP array of 1024 bytes
• Block Protection:
• Status Register bits to control protection against program or erase of a contiguous range of sectors
• Hardware and software control options
• Advanced Sector Protection (ASP)
• Individual sector protection controlled by boot code or password
• Cypress 65 nm MirrorBit Technology with Eclipse Architecture
• Temperature Range / Grade:
• Industrial (-40°C to +85°C)
• Industrial Plus (-40°C to +105°C)
• Automotive AEC-Q100 Grade 3 (-40°C to +85°C)
• Automotive AEC-Q100 Grade 2 (-40°C to +105°C)
• Automotive AEC-Q100 Grade 1 (-40°C to +125°C)