SN74AHC138DR

The 'AHC138 decoders/demultiplexers are designed for high- performance memory- decoding and data- routing applications that require very short propagation/delay times. In high- performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high- speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible. The conditions at the binary- select inputs and the three enable inputs select one of eight output lines. Two active- low and one active- high enable inputs reduce the need for external gates or inverters when expanding. A 24- line decoder can be implemented without external inverters, and a 32- line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.

Applications

• High-performance memory decoding systems
• High-speed data transmission and data routing systems
• Decoding expansion applications
• Demultiplexing applications

Key features

• Supply voltage operating range: 2V to 5.5V
• Designed for high-speed memory decoding and data transmission systems
• Integrated three enable inputs for simplified cascading and data reception
• Latch-up performance exceeds 250mA, compliant with JESD 17
• ESD protection compliant with JESD 22
• Human Body Model 2000V (A114-A) ESD compliant
• Machine Model 200V (A115-A) ESD compliant
• Charged Device Model 1000V (C101) ESD compliant
• NC pins have no internal connection
• Multiple package options available