SN74AUP1G00DRLR

Schmitt trigger 800mV~3.6V 6.5ns@3.3V,30pF 500nA SOT-5X3-5 Gates and Inverters RoHS

SOT-5X3-5ROHS3 CompliantActive

Low-Power Single 2-Input Positive-NAND Gate

Every Order Guarantee

100% Authentic · 30-Day Return or Replacement · policy

195 in stock

#C2872330

Stock & price checked 6 days ago

Quantity (min 5, multiples of 5)

5 × ₹27.54

₹137.70

excl. GST

₹162.49 incl. 18% GST

SN74AUP1G00DRLR

₹137.70 for 5 + GST

Specifications

Input Type: Schmitt trigger
Logic Family: 74AUP Series
Voltage - Supply: 800mV~3.6V
Output Logic Level - Low: 310mV;440mV
Propagation Delay: 6.5ns@3.3V,30pF
Features: Live insertion protection;Local shutdown mode;Rear drive protection;Overvoltage-tolerant input
Operating Temperature: -40℃~+85℃
Input Logic Level - Low: 700mV~900mV
Input Logic Level - High: 1.6V~2V
Output Logic Level - High: 2.6V;2.72V
Quiescent Current(Iq): 500nA
Current - Output High(IOH): 4mA
Number of Channels: 1;2
Current - Output Low(IOL): 4mA

This single 2-input positive-NAND gate performs the Boolean function Y(overline)=A x B or Y = A(overline) + B(overline) in positive logic.

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ESD Performance Tested Per JESD 22: 2000-V Human-Body Model (A114-B, Class II), 1000-V Charged-Device Model (C101)
Available in the Ultra Small 0.64 mm² Package (DPW) with 0.5 mm Pitch
Low Static-Power Consumption (Icc = 0.9 μA Max)
Low Dynamic-Power Consumption (ΔCpd = 4 pF Typical at 3.3 V)
Low Input Capacitance (Ci = 1.5 pF Typical)
Low Noise Overshoot and Undershoot < 10% of VCC
Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at Input (Vhys = 250 mV Typical at 3.3 V)
Wide Operating VCC Range of 0.8 V to 3.6 V
Optimized for 3.3-V Operation
3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
tpd = 4.8 ns Maximum at 3.3 V
Suitable for Point-to-Point Applications
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II