SN74AUP1G80DBVR

The AUP family assures a low static- and dynamic-power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in increased battery life. This is a single positive-edge-triggered D-type flipflop. When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. NanoStar package technology uses the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.

Applications

• Home Automation
• Factory Automation
• Test and Measurement
• Enterprise Switching
• Telecom Infrastructure
• Personal Electronics
• White Goods

Key features

• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Performance Tested Per JESD 22: 2000-V Human-Body Model (A114-B, Class II), 1000-V Charged-Device Model (C101)
• Available in the Texas Instruments NanoStar Package
• Low Static-Power Consumption (IC C = 0.9 μA Maximum)
• Low Dynamic-Power Consumption (Δ'Cpd = 4.3 pF Typical at 3.3 V)
• Low Input Capacitance ('Ci = 1.5 pF Typical)
• Low Noise – Overshoot and Undershoot < 10% of VCC
• Ioff Supports Partial-Power-Down Mode Operation
• Schmitt-Trigger Action Allows Slow Input Transition and Better Switching Noise Immunity at the Input (Vhys = 250 mV Typical at 3.3 V)
• Wide Operating VCC Range of 0.8 V to 3.6 V
• Optimized for 3.3-V Operation
• 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
• Δfpd = 4.4 ns Maximum at 3.3 V
• Suitable for Point-to-Point Applications