SN74F74DR

Package options include plastic small-outline, ceramic chip carrier, and standard plastic and ceramic 300-mil DIP packages. These devices contain two independent positive-edge-triggered D-type flip-flops. When the preset (PRE) or clear (CLR) input is low, the outputs are set or reset regardless of the other input levels. When PRE and CLR are inactive (high), data at the D input that meets setup time requirements is transferred to the outputs on the rising edge of the clock pulse. Clock triggering occurs at a specific voltage level and is not directly related to the rise time of the clock pulse. After the hold time interval ends, data at the D input can change without affecting the output levels. The SN74F74 operates over a temperature range of 0℃ to 70℃.