SN74HC174DR

These positive-edge-triggered D-type flip-flops feature a direct clear (CLR) input. Data (D) input information that meets the setup time requirements is transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a specific voltage level and is not directly related to the transition time of the CLK rising edge. When CLK is high or low, the D input has no effect on the outputs.

Applications

• Buffer/Storage Registers Shift Registers
• Pattern Generators

Key features

• Wide Operating Voltage Range of δ₂V for all cases to 6 V
• Outputs Can Drive Up To 10 LSTTL Loads
• Low Power Consumption, 80-μA Max ICC
• Typical propagation delay time (tₚd) = 14 ns
• ±4-mA Output Drive at 5 V
• Low Input Current of 1 μA Max
• Contain Six Flip-Flops With Single-Rail Outputs