Varnitronics
SN74HCT574DWR TI
TI

SN74HCT574DWR

4.5V~5.5V 8 1 47ns@5.5V,150pF SOIC-20-300mil Flip Flops RoHS

SOIC-20-300milROHS3 CompliantActive

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

Manufacturer
TI
Manufacturer part #
SN74HCT574DWR
Store part #
C6788
Package / case
SOIC-20-300mil
Category
Flip Flops
Packaging
Tape & Reel (TR)
Datasheet (PDF)

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100% Authentic · 30-Day Return or Replacement · policy

1,899 in stock

#C6788

Stock & price checked 5 days ago

QuantityUnit pricePack price
1+₹92.64₹92.64
10+₹74.59₹745.90
30+₹65.46₹1,963.80
100+₹56.55₹5,655.00
500+₹51.11₹25,555.00
1,000+₹48.28₹48,280.00

1 × ₹92.64

₹92.64

excl. GST

₹109.32 incl. 18% GST

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  • Standard pack: 2,000 per reel

SN74HCT574DWR

₹92.64 for 1 + GST

Specifications

Voltage - Supply
4.5V~5.5V
Number of Bits per Element
8
Output Type
Tri-State
Operating Temperature
-40℃~+85℃
Series
74HCT Series
Number of Elements
1
Current - Output High(IOH)
6mA
Current - Output Low(IOL)
6mA
Setup Time
23ns
Quiescent Current
8uA
Hold Time
5ns
Propagation Delay
47ns@5.5V,150pF
Trigger Type
Rising Edge

Packaging & compliance

RoHS
ROHS3 Compliant
Lifecycle
Active
ECCN
EAR99
Packaging
Tape & Reel (TR)
Standard pack
2,000 / Reel
Sold per
Piece
Minimum order
1
Unit weight
0.747 g

Overview

These octal edge-triggered D-type flip-flops feature 3-state outputs designed specifically for bus driving. The ’HCT574 devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight flip-flops enter data on the low-to-high transition of the clock (CLK) input. A buffered output-enable (overline{OE})) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

Applications

  • Buffer register implementation
  • I/O port implementation
  • Bidirectional bus driver implementation
  • Working register implementation

Key features

  • Operating Voltage Range of 4.5 V to 5.5 V
  • High-Current 3-State Noninverting Outputs Drive Bus Lines Directly or Up To 15 LSTTL Loads
  • Low Power Consumption, 80 μA Max ICC
  • Typical t_pd=22ns
  • ±6 - mA Output Drive at 5 V
  • Low Input Current of 1 μA Max
  • Inputs Are TTL-Voltage Compatible Bus-Structured Pinout

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