SN74LV573ADGVR
D Latch 2V~5.5V 8 1ns TVSOP-20-4.4mm Latches RoHS
OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
Every Order Guarantee
100% Authentic · 30-Day Return or Replacement · policy
3,999 in stock
#C2675325
Stock & price checked 6 days ago
| Quantity | Unit price | Pack price |
|---|---|---|
| 1+ | ₹99.87 | ₹99.87 |
| 10+ | ₹79.90 | ₹799.00 |
| 30+ | ₹69.91 | ₹2,097.30 |
| 100+ | ₹59.92 | ₹5,992.00 |
| 500+ | ₹54.06 | ₹27,030.00 |
| 1,000+ | ₹51.03 | ₹51,030.00 |
1 × ₹99.87
₹99.87
excl. GST
₹117.85 incl. 18% GST
- Dispatch in 7–10 working days
- GST invoice with every order
- Standard pack: 2,000 per reel
SN74LV573ADGVR
₹99.87 for 1 + GST
Specifications
- Quiescent Current
- 20uA
- Series
- 74LV
- Logic Type
- D Latch
- Voltage - Supply
- 2V~5.5V
- Operating Temperature
- -40℃~+85℃
- Current - Output Low(IOL)
- 16mA
- Output Type
- Tri-State
- Setup Time
- 3.5ns
- Number of Gates
- 8
- Current - Output High(IOH)
- 16mA
- Hold Time
- 1.5ns
- Propagation Delay
- 1ns
Packaging & compliance
- RoHS
- ROHS3 Compliant
- Lifecycle
- Active
- ECCN
- EAR99
- Packaging
- Tape & Reel (TR)
- Standard pack
- 2,000 / Reel
- Sold per
- Piece
- Minimum order
- 1
- Unit weight
- 0.001 g
Overview
devices are octal transparent D-type latches designed for 2-V to 5.5-V VCC operation. These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. This device is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
Applications
- buffer registers
- I/O ports
- bidirectional bus drivers
- working registers
Key features
- 2-V to 5.5-V VCC Operation
- Max tpd of 8 ns at 5 V
- Typical V₀ₗₚ (Output Ground Bounce) < 0.8 V at VCC = 3.3V, TA = 25℃
- Typical V₀ₕᵥ (Output V₀ₕ Undershoot) > 2.3 V at VCC = 3.3V, TA = 25℃
- Support Mixed-Mode Voltage Operation on All Ports
- Ioff Supports Partial-Power-Down Mode Operation
- Latch-Up Performance Exceeds 250 mA Per JESD 17
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
Alternatives
Similar parts — check the datasheet before substituting.
| Part | Manufacturer | Package | Stock | Price from (excl. GST) | Action | |
|---|---|---|---|---|---|---|
![]() | SN74AHC373DGVR#C2652984TI · TVSOP-20-4.4mm | TI | TVSOP-20-4.4mm | 100 | ₹138.40 · 100 in stock | View |
| SN74LV373ADGVR#C1880228TI · TVSOP-20-4.4mm | TI | TVSOP-20-4.4mm | On request | Price on request | Quote | |
| SN74AHC573DGVR#C2867112TI · TVSOP-20-4.4mm | TI | TVSOP-20-4.4mm | On request | Price on request | Quote | |
Same category






