SN74LV573ATPWR

The SN74LV573AT is an 8-bit transparent D-type latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs latch the logic levels of the D inputs. The buffered output-enable (OE) input places the eight outputs in either a normal logic state (high or low) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and enhanced drive capability allow this device to drive bus lines without interface or pullup components. To ensure the high-impedance state during power up or power down, OE must be connected through a pullup resistor to VCC; the minimum value of the resistor is determined by the current-sinking capability of the driver. OE does not affect the internal operation of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging reverse current from flowing through the device when it is powered down.

Key features

• TTL-compatible inputs
• 4.5 V to 5.5 V VCC operation
• Typical propagation delay tpd of 5.1 ns at 5 V
• Typical output ground bounce VOLP < 0.8 V at VCC = 5 V, TA = 25℃
• Typical output VOH undershoot VOHV > 2.3 V at VCC = 5 V, TA = 25℃
• Mixed-mode voltage operation on all ports
• Ioff supports partial power-down mode operation
• Latch-up performance exceeds 250 mA per JESD 17
• ESD protection exceeds JESD 22
• Human Body Model (A114-A) ESD protection: 2000 V
• Machine Model (A115-A) ESD protection: 200 V
• Charged Device Model (C101) ESD protection: 1000 V