SN74LVC2G02DCTR

Available in the NanoFree™ Package Supports 5-V Vcc Operation Inputs Accept Voltages to 5.5 V Max tpd of 4.9 ns at 3.3 V Low Power Consumption, 10 - μA Max ICC ±24 - mA Output Drive at 3.3 V Typical VoLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25 ℃ Typical V0HV (Output VoH Undershoot) > 2 V at VCC = 3.3 V, TA = 25 ℃ Ioff Supports Partial - Power - Down Mode Operation Latch - Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000 - V Human - Body Model (A114 - A) 1000 - V Charged - Device Model (C101) This dual 2 - input positive - NOR gate is designed for 1.65 - V to 5.5 - VCC operation. The SN74LVC2G02 performs the Boolean function Y = (A + B) (overline) or Y = A (overline) · B (overline) in positive logic. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial - power - down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

Key features

• NanoFree package available
• 5V Vcc operation supported
• Inputs tolerant up to 5.5V
• Maximum propagation delay tpd of 4.9ns at 3.3V
• Low power consumption, maximum supply current Icc of 10μA
• Output drive current ±24mA at 3.3V
• Typical output ground bounce VOLP less than 0.8V at Vcc=3.3V, TA=25℃
• Typical output VOH undershoot VOHV greater than 2V at Vcc=3.3V, TA=25℃
• Ioff supports partial power-down mode operation
• Latch-up performance exceeds 100mA, compliant with JESD 78 Class II
• ESD protection compliant with JESD 22
• HBM ESD protection up to 2000V, CDM ESD protection up to 1000V
• Integrated limited ESD protection; precautions required to prevent electrostatic damage to MOS gates during storage or handling