UC3842BS

3842 is a high-performance fixed-frequency current-mode controller designed for off-line and DC-DC converter applications, offering designers a low-cost solution with minimal external component requirements. This IC incorporates an oscillator trimmed for precise duty cycle control, a temperature-compensated reference, a high-gain error amplifier, a current-sensing comparator, and a high-current totem-pole output stage ideally suited for driving power MOSFETs. Built-in protection features include input and undervoltage lockout, cycle-by-cycle current limiting, programmable output dead time, and a latch for single-pulse metering. During layout, careful attention to grounding techniques is required when high peak currents associated with capacitive loads are present. The timing capacitor and bypass capacitors must be mounted as close as possible to Pin 5 and returned to a single-point ground. When the controller enters the undervoltage shutdown state, the output driver goes to a high-impedance state. In this condition, Pin 6 must be returned to ground through a bleed resistor to prevent leakage currents from falsely triggering the power switch. Peak current is defined as: I_S(MAX) ≈ 1.0V / R_S, and a small RC filter network is typically required to suppress switching transients. The oscillator timing capacitor CT is charged through RT from VREF and discharged by an internal current source. During the discharge interval, an internal clock signal drives the output low. Both the oscillator frequency and maximum duty cycle are determined by the selection of RT and CT. The charge and discharge times are given by: t_c ≈ 0.55 × RT × CT; t_d = RT × CT × ln((0.063 × RT - 2.7) / (0.063 × RT - 4)); the resulting frequency is: f = (t_c + t_d)^-1; when RT > 5kΩ, f ≈ 1.8 / (RT × CT). Shutdown of the 3842 can be accomplished by two methods: raising Pin 3 voltage above 1V, or pulling Pin 1 voltage low to near ground potential (within two diode forward voltage drops). Either method causes the PWM comparator output to go high, thereby overriding the PWM latch reset and holding the output low until the next clock cycle after the shutdown signal is removed. An example of an externally latched shutdown employs a thyristor, which resets when the supply voltage VCC falls below the undervoltage lockout threshold. At that point, the reference shuts down, allowing the thyristor to reset. A portion of the oscillator ramp can be summed into the current-sense signal to implement slope compensation in converters requiring duty cycles greater than 50%. Capacitor C and resistor R2 form a filter to suppress leading-edge switching spikes.

Applications

• Inverter power supplies
• High-power high-frequency switching power supplies
• DC pulse-width modulation speed control systems
• UPS power supplies
• DC/DC converters
• High-power chargers

Key features

• Undervoltage lockout circuit
• Low startup current (< 0.3mA)
• Stable internal bandgap reference voltage source
• High-current totem-pole output (drive current up to 1A)
• Operating frequency up to 500kHz
• Automatic feed-forward compensation circuit
• Pulse-by-pulse current limiting
• Enhanced load transient response