ZSBM1006QN

The ZSBM1006 incorporates all the features typically required in portable, low-power medical, sports, and fitness ECG applications. With high integration and excellent performance, the ZSBM1006 enables scalable medical instrument systems with advantages in small size, low power consumption, and overall cost. The ZSBM1006 features 1 high-resolution channel capable of operating at up to 16ksps. The device supports programmable sample rates and bandwidth, allowing users to optimize configuration for performance and power consumption. All input pins include an EMI filter. In addition, the ZSBM1006 incorporates a configurable integrated interrupt system that enables the following functions: - DC lead-off detection - FIFO threshold detection / overflow / underflow anomaly detection - Instant data readout The device comes in a 4mm×4mm×0.65mm, 16-pin QFN package with an operating temperature range of -40°C ~ 85°C. The ZSBM1006 is a fully integrated signal chain for heart rate band applications. It features a low-power, 16-bit resolution ECG channel, along with DC lead-off detection and right leg drive capability. The ZSBM1006 includes an analog front-end for converting differential analog voltages to digital signals. Each analog front-end comprises a Sigma-Delta Modulator (SDM) and a digital filter. The analog front-end can be activated by setting the OP_EN register to 1, and deactivated by setting it to 0. The SDM acquires a pair of input signals configured through a switch array and converts them into a digital bit stream with high-frequency noise, which is further processed by a programmable digital filter to obtain a high-resolution digital signal. The SDM operates at a clock frequency of 125kHz, which can be generated by internal configuration. The SDM offers 2 oversampling ratio (OSR) options: 1024 (default) and 512. The OSR is configured via register R1_RATE_CH0_ECG. A programmable digital filter follows the SDM to reconstruct the signal from the output bit stream. The filter consists of two stages of programmable SINC filters, each being a fifth-order SINC filter. The SINC filter decimation ratio R0 is fixed at 64, while R1 is programmable. Each stage further filters and decimates the bit stream, reducing the output data rate (ODR) and bandwidth (BW) while increasing resolution. After the first stage, a 16-bit digital signal with higher ODR and BW is available. The ZSBM1006's programmable digital filter provides two ODR and bandwidth configurations to achieve different levels of performance and power consumption. As the second-stage decimation (R1) increases, the ECG ODR and BW decrease. A higher R1 value is recommended for ECG signal detection. The R1 decimation ratio for each channel can be set using R1_RATE_CH0_ECG. The low-pass filter frequency response of the ECG SINC filter produces an associated settling time due to its output response to a step input signal. This settling time depends on the filter order, its differential delay, and the channel ODR. Therefore, the minimum settling time for the ECG channel is: t_S - ECG = 320×R1 / fs, where: fs is the modulator clock frequency; R1 is 1025/512, determined by the R1_RATE_CH0_ECG register configuration. The ZSBM1006 configures an impedance to RLDOUT at both input terminals for each ADC. The resistance value can be adjusted via INPUT_RES_CH0[3:0] over a range of approximately 20MΩ to 10GΩ. This function requires both RLD_EN and INPUT_RES_EN to be enabled simultaneously. The ECG data for each ADC channel can be offset-corrected via ADC_OFFSET_CH0[15:0]. The right leg drive (RLD) circuit is an amplifier with a certain gain that drives an output electrode connected to the body, forming a common-mode loop between the chip and the body, thereby biasing the other input electrodes to the desired common-mode voltage range. The voltages from multiple input electrodes pass through a common-mode sensing circuit, and the resulting common-mode voltage is compared with the input voltage at RLDIN (typically the desired common-mode voltage of the ECG system). The difference is amplified and output to the RLDOUT pin. In addition to biasing the common-mode level, the high common-mode loop gain also suppresses common-mode interference introduced into the loop from external sources (such as power line frequency interference), thereby improving the system CMRR. The RLD amplifier has a certain load drive capability, similar to a cable shield driver. By configuring registers RLD_CAP[4:0] and RLD_CURR[3:0], an optimal trade-off between drive capability and power consumption can be achieved. Since the input/output of the RLD amplifier and the output of the cable shield driver are all accessible via pins, users can configure the combination of external resistors and capacitors around the RLD amplifier at the board level to achieve the desired gain and bandwidth.

Applications

• Sports & fitness (heart rate and ECG)

Key features

• One 16-bit digital heart rate and ECG channel
• EMI-resistant inputs
• Low power consumption: 0.2mW per channel
• Equivalent input noise: 4.4μVrms (40Hz bandwidth)
• Input bias current: 65pA
• Data rate: up to 0.250Ksps
• Differential input voltage range: ±500mV
• Analog supply voltage: 2.2V to 5.5V
• Digital I/O supply voltage: 1.8V to 5.5V
• Right leg drive amplifier
• DC lead-off detection
• Configurable integrated interrupt system
• On-chip oscillator and reference
• Flexible power-down and standby modes