74ALVC74D,118

The 74ALVC74 is a dual positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q(overline) outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. Schmitt trigger action on all inputs makes the device tolerant of slow rise and fall times. This device is fully specified for partial power down applications using IOFF. The l(OFF) circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Applications

• Data processing
• Signal synchronization
• Timing control
• Low-power applications
• Partial power-down mode operation
• Direct TTL-level interface
• Input tolerance for slow rise and fall times

Key features

• Wide supply voltage range from 1.65 V to 3.6 V
• CMOS low power dissipation
• Overvoltage tolerant inputs to 3.6 V
• Direct interface with TTL levels
• IOFF circuitry provides partial Power-down mode operation
• Latch-up performance exceeds 250 mA per JESD78 Class II.A
• Complies with JEDEC standard:
• JESD8-7 (1.65 to 1.95 V)
• JESD8-5 (2.3 to 2.7 V)
• JESD8C/JESD36 (2.7 V to 3.6 V)
• ESD protection:
• HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
• CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
• Specified from -40 °C to +85 °C and from -40 °C to +125 °C