74AUP2G86DC,125

Schmitt trigger 800mV~3.6V 9.2ns@3V,30pF 1.4uA VSSOP-8-0.5mm Gates and Inverters RoHS

VSSOP-8-0.5mmROHS3 CompliantActive

Low-power dual 2-input EXCLUSIVE-OR gate

Manufacturer: Nexperia
Manufacturer part #: 74AUP2G86DC,125
Store part #: C546155
Package / case: VSSOP-8-0.5mm
Category: Gates and Inverters
Packaging: Tape & Reel (TR)

Datasheet (PDF)

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2,900 in stock

#C546155

Stock & price checked 6 days ago

Quantity	Unit price	Pack price
1+	₹57.83	₹57.83
10+	₹45.63	₹456.30
30+	₹40.27	₹1,208.10
100+	₹33.84	₹3,384.00
500+	₹30.85	₹15,425.00
1,000+	₹29.13	₹29,130.00

Quantity (min 1)

1 × ₹57.83

₹57.83

excl. GST

₹68.24 incl. 18% GST

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Standard pack: 3,000 per reel

74AUP2G86DC,125

₹57.83 for 1 + GST

Specifications

Input Type: Schmitt trigger
Logic Family: 74AUP
Voltage - Supply: 800mV~3.6V
Propagation Delay: 9.2ns@3V,30pF
Features: Local shutdown mode
Operating Temperature: -40℃~+125℃
Quiescent Current(Iq): 1.4uA
Number of Channels: 2;2
Current - Output High(IOH): 4mA
Current - Output Low(IOL): 4mA

Packaging & compliance

RoHS: ROHS3 Compliant
Lifecycle: Active
ECCN: EAR99
Packaging: Tape & Reel (TR)
Standard pack: 3,000 / Reel
Sold per: Piece
Minimum order: 1
Unit weight: 0.041 g

Overview

The 74AUP2G86 provides the dual 2-input EXCLUSIVE-OR function. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down.

Key features

Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V), JESD8-11 (0.9 V to 1.65 V), JESD8-7 (1.2 V to 1.95 V), JESD8-5 (1.8 V to 2.7 V), JESD8-B (2.7 V to 3.6 V)
Low static power consumption; ICC = 0.9 μA (maximum)
Latch-up performance exceeds 100 mA per JESD78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10% of VCC
IOFF circuitry provides partial Power-down mode operation
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Multiple package options
Specified from -40 ℃ to +85 ℃ and -40 ℃ to +125 ℃
Low-power dual 2-input EXCLUSIVE-OR gate