74HC595D-DW

The 74HC595D is a high-speed silicon gate CMOS device with pin compatibility with Low-Power Schottky TTL circuits. The device conforms to JEDEC standard 7A. It consists of an 8-bit shift register and a storage register with 3-state outputs. The shift register and storage register have separate clocks. Data is shifted into the shift register on the rising edge of the shift clock and transferred from the shift register to the storage register on the rising edge of the storage clock. If the two clocks are connected together, the data in the shift register will always be one clock pulse ahead of the data in the storage register. The shift register has a serial data input, a serial output for cascading, and an active LOW asynchronous master reset. The storage register provides 8-bit parallel 3-state bus driver outputs. When the output enable is LOW, the outputs are active; when the output enable is HIGH, the outputs are in a high-impedance state.

Applications

• Serial-to-parallel conversion
• Remote control hold register

Key features

• 8-bit serial input
• 8-bit serial or parallel output
• Storage register with tri-state outputs
• Shift register with direct clear
• Typical shift frequency: 100MHz
• ESD protection