74HC595PW

The 74HC595 and 74HCT595 are 8-bit serial-in, serial or parallel-out shift registers with output latches and 3-state outputs. The shift register and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) for cascading, along with an asynchronous reset $\overline{MR}$ input. $\overline{MR}$ LOW resets the shift register. Data is shifted on the LOW-to-HIGH transition of the SHCP input. Data in the shift register is transferred to the storage register on the LOW-to-HIGH transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. When the output enable input ($\overline{OE}$) is LOW, the data in the storage register appears at the outputs. When $\overline{OE}$ is HIGH, the outputs are in the high-impedance OFF state. Operation of the $\overline{OE}$ input does not affect the state of the registers. Inputs include clamping diodes, which allow input interfacing to voltages exceeding VCC using current-limiting resistors.

Applications

• Serial-to-parallel data conversion
• Remote control hold register

Key features

• Wide supply voltage range: 2.7 V ~ 6.0 V
• High noise immunity
• CMOS low power consumption
• 8-bit serial input
• 8-bit serial or parallel output
• Storage register with 3-state outputs
• Shift register with direct clear
• Latch performance exceeds 250 mA
• JEDEC compliant: JESD8C (2.7 V ~ 3.6 V) and JESD7A (2.7 V ~ 6.0 V)
• Input levels: CMOS for 74HC595; TTL for 74HCT595
• ESD protection: HBM ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 3500 V; CDM ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 2000 V
• Multiple package options
• Operating temperature range: -40 °C ~ +85 °C and -40 °C ~ +125 °C