Varnitronics
74LVC1G02GW MDD(Microdiode Semiconductor)
MDD(Microdiode Semiconductor)

74LVC1G02GW

Schmitt trigger 1.65V~5.5V 100nA SOT-353 Gates and Inverters

SOT-353RoHSActive
Manufacturer part #
74LVC1G02GW
Store part #
C52953351
Package / case
SOT-353
Packaging
Tape & Reel (TR)
Datasheet (PDF)

Every Order Guarantee

100% Authentic · 30-Day Return or Replacement · policy

2,920 in stock

#C52953351

Stock & price checked 6 days ago

QuantityUnit pricePack price
10+₹9.50₹95.00
100+₹7.49₹749.00
300+₹6.48₹1,944.00
3,000+₹5.73₹17,190.00
6,000+₹5.12₹30,720.00
9,000+₹4.83₹43,470.00

10 × ₹9.50

₹95.00

excl. GST

₹112.10 incl. 18% GST

Need volume or a scheduled delivery? Request a quote
  • Dispatch in 7–10 working days
  • GST invoice with every order
  • Standard pack: 3,000 per reel

74LVC1G02GW

₹95.00 for 10 + GST

Specifications

Input Type
Schmitt trigger
Logic Family
74LVC
Voltage - Supply
1.65V~5.5V
Propagation Delay
15.9ns@1.65V,30pF;8.6ns@2.3V,30pF;6ns@3V,50pF;3.6ns@4.5V,50pF
Output Logic Level - Low
100mV;450mV;600mV;700mV;800mV
Operating Temperature
-40℃~+125℃
Features
Local shutdown mode;Overvoltage-tolerant input
Quiescent Current(Iq)
100nA
Number of Channels
1;2
Current - Output High(IOH)
32mA
Current - Output Low(IOL)
32mA

Packaging & compliance

RoHS
RoHS
Lifecycle
Active
Packaging
Tape & Reel (TR)
Standard pack
3,000 / Reel
Sold per
Piece
Minimum order
10 (multiples of 10)
Unit weight
0.074 g

Overview

The 74LVC1G02 is a single 2-input NOR gate. Its inputs can be driven by 3.3V or 5V devices. This feature allows the device to be used as a level translator in mixed 3.3V and 5V environments. All inputs include Schmitt-trigger action, enabling the circuit to tolerate slower input rise and fall times. The device is fully specified for partial power-down applications using IOFF. The IOFF circuit disables the outputs, preventing potentially destructive backflow current through the device when it is powered down.

Key features

  • Wide supply voltage range: 1.65V to 5.5V
  • Input overvoltage tolerance up to 5.5V
  • High noise immunity
  • CMOS low power consumption
  • IOFF circuit for partial power-down mode operation
  • Output drive capability ±24mA (at VCC = 3.0V)
  • Latch-up performance exceeds 100mA
  • Direct TTL-level interface compatible
  • Compliant with JEDEC standards: JESD8-7 (1.65V to 1.95V), JESD8-5 (2.3V to 2.7V), JESD8C (2.7V to 3.6V), JESD36 (4.5V to 5.5V)
  • ESD protection: HBM ANSI/ESDA/JEDEC JS-001 Class 3B exceeds 8000V; MM JESD22-A115C Class C exceeds 550V; CDM ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 2000V
  • Multiple package options
  • Single 2-input NOR gate

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