74LVC1G08GS

The 74LVC1G08 is a single 2-input AND gate. The inputs can be driven by 3.3 V or 5 V devices. This feature allows these devices to be used as translators in mixed 3.3 V and 5 V applications. Schmitt-trigger action on all inputs enables the circuit to tolerate slower input rise and fall times. The device is fully specified for partial power-down applications using IOFF. The IOFF circuit disables the output, preventing damaging backflow current through the device when it is powered down.

Key features

• Wide supply voltage range: 1.65 V to 5.5 V
• High noise immunity
• ±24 mA output drive (VCC = 3.0 V)
• CMOS low power consumption
• Direct TTL-level interface
• Input overvoltage tolerance up to 5.5 V
• IOFF circuit for partial power-down mode operation
• Latch-up performance exceeds 100 mA
• JEDEC standard compliant:
• JESD8-7 (1.65 V to 1.95 V)
• JESD8-5 (2.3 V to 2.7 V)
• JESD8C (2.7 V to 3.6 V)
• JESD36 (4.5 V to 5.5 V)
• ESD protection:
• HBM ANSI/ESDA/JEDEC JS-001 Class 3B exceeds 8000 V
• MM JESD22-A115C Class C exceeds 550 V
• CDM ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 2000 V
• Multiple package options