MDD(Microdiode Semiconductor)

74LVC2G04GW

Schmitt trigger 1.65V~5.5V 2ns@5.5V,50pF 4uA 2 SOT-363 Gates and Inverters

SOT-363RoHSActive

Manufacturer: MDD(Microdiode Semiconductor)
Manufacturer part #: 74LVC2G04GW
Store part #: C52140491
Package / case: SOT-363
Category: Gates and Inverters
Packaging: Tape & Reel (TR)

Datasheet (PDF)

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4,223 in stock

#C52140491

Stock & price checked 6 days ago

Quantity	Unit price	Pack price
1+	₹16.59	₹16.59
10+	₹13.07	₹130.70
30+	₹11.32	₹339.60
100+	₹10.00	₹1,000.00
500+	₹8.96	₹4,480.00
1,000+	₹8.43	₹8,430.00

Quantity (min 1)

1 × ₹16.59

₹16.59

excl. GST

₹19.58 incl. 18% GST

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Standard pack: 3,000 per reel

74LVC2G04GW

₹16.59 for 1 + GST

Specifications

output type: Push-pull
Input Type: Schmitt trigger
Logic Family: 74LVC
Voltage - Supply: 1.65V~5.5V
Propagation Delay: 2ns@5.5V,50pF
Output Logic Level - Low: 800mV
Features: Power shutdown protection;Noise suppression function
Input Logic Level - Low: 700mV;800mV
Input Logic Level - High: 1.7V~2V
Operating Temperature: -40℃~+125℃
Output Logic Level - High: 2V
Quiescent Current(Iq): 4uA
Current - Output High(IOH): 32mA
Number of Channels: 2
Current - Output Low(IOL): 32mA

Packaging & compliance

RoHS: RoHS
Lifecycle: Active
Packaging: Tape & Reel (TR)
Standard pack: 3,000 / Reel
Sold per: Piece
Minimum order: 1
Unit weight: 0.074 g

Overview

The 74LVC2G04 is a dual inverter. Its inputs can be driven by 3.3V or 5V devices. This feature allows the device to be used as a level translator in mixed 3.3V and 5V environments. All inputs incorporate Schmitt-trigger action, making the circuit tolerant of slower input rise and fall times. The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the outputs, preventing damaging backflow current when the device is powered down.

Key features

Wide supply voltage range: 1.65V to 5.5V
Input overvoltage tolerance up to 5.5V
High noise immunity
Output drive capability ±24 mA (VCC = 3.0 V)
CMOS low power consumption
Direct TTL-level interface capability
IOFF circuit for partial power-down mode operation
Latch-up performance exceeds 100 mA
JEDEC compliant: JESD8-7 (1.65 V to 1.95 V), JESD8-5 (2.3 V to 2.7 V), JESD8C (2.7 V to 3.6 V), JESD36 (4.6 V to 5.5 V)
ESD protection: HBM ANSI/ESDA/JEDEC JS-001 Class 3B exceeds 8000 V; MM JESD22-A115C Class C exceeds 550 V; CDM ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 2000 V
Multiple package options