Varnitronics
74LVC2G14GM MDD(Microdiode Semiconductor)
MDD(Microdiode Semiconductor)

74LVC2G14GM

Schmitt trigger 1.65V~5.5V 2.9ns@5V,50pF 4uA 2 DFN-6L(1x1.5) Gates and Inverters

DFN-6L(1x1.5)RoHSActive
Manufacturer part #
74LVC2G14GM
Store part #
C53552930
Package / case
DFN-6L(1x1.5)
Packaging
Tape & Reel (TR)
Datasheet (PDF)

Every Order Guarantee

100% Authentic · 30-Day Return or Replacement · policy

2,285 in stock

#C53552930

Stock & price checked 5 days ago

QuantityUnit pricePack price
5+₹15.58₹77.90
50+₹12.28₹614.00
150+₹10.64₹1,596.00
500+₹9.39₹4,695.00
3,000+₹8.40₹25,200.00
6,000+₹7.91₹47,460.00

5 × ₹15.58

₹77.90

excl. GST

₹91.92 incl. 18% GST

Need volume or a scheduled delivery? Request a quote
  • Dispatch in 7–10 working days
  • GST invoice with every order
  • Standard pack: 3,000 per reel

74LVC2G14GM

₹77.90 for 5 + GST

Specifications

Input Type
Schmitt trigger
Logic Family
74LVC
Voltage - Supply
1.65V~5.5V
Propagation Delay
2.9ns@5V,50pF
Output Logic Level - Low
100mV;450mV;300mV;400mV;550mV
Features
Power shutdown protection;Noise suppression function
Operating Temperature
-40℃~+125℃
Output Logic Level - High
1.2V;1.9V;2.2V;2.3V;3.8V
Quiescent Current(Iq)
4uA
Current - Output High(IOH)
32mA
Number of Channels
2
Current - Output Low(IOL)
32mA

Packaging & compliance

RoHS
RoHS
Lifecycle
Active
Packaging
Tape & Reel (TR)
Standard pack
3,000 / Reel
Sold per
Piece
Minimum order
5 (multiples of 5)
Unit weight
0.07 g

Overview

The 74LVC2G14 is a dual inverter with Schmitt-trigger inputs. The inputs can be driven by 3.3V or 5V devices. This feature allows these devices to be used as level translators in mixed 3.3V/5V environments. The device is fully specified for partial power-down applications using IOFF. The IOFF circuit disables the outputs, preventing potentially damaging backflow current through the device when it is powered down.

Key features

  • Wide supply voltage range: 1.65V to 5.5V
  • Input overvoltage tolerance up to 5.5V
  • High noise immunity
  • ±24mA output drive (VCC = 3.0V)
  • CMOS low power consumption
  • Latch-up performance exceeds 100mA
  • Direct TTL-level interface compatible
  • IOFF circuit for partial power-down mode operation
  • Unrestricted rise and fall times
  • JEDEC compliant:
  • JESD8-7 (1.65V to 1.95V)
  • JESD8-5 (2.3V to 2.7V)
  • JESD8C (2.7V to 3.6V)
  • JESD36 (4.5V to 5.5V)
  • ESD protection:
  • HBM ANSI/ESDA/JEDEC JS-001 Class 3B exceeds 8000V
  • MM JESD22-A115C Class C exceeds 550V
  • CDM ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 2000V
  • Multiple package options

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