Varnitronics
74LVC2G14GW MDD(Microdiode Semiconductor)
MDD(Microdiode Semiconductor)

74LVC2G14GW

Schmitt trigger 1.65V~5.5V 2.9ns@5V,50pF 4uA 2 SOT-363 Gates and Inverters

SOT-363RoHSActive
Manufacturer part #
74LVC2G14GW
Store part #
C52953354
Package / case
SOT-363
Packaging
Tape & Reel (TR)
Datasheet (PDF)

Every Order Guarantee

100% Authentic · 30-Day Return or Replacement · policy

2,460 in stock

#C52953354

Stock & price checked 6 days ago

QuantityUnit pricePack price
10+₹9.50₹95.00
100+₹7.49₹749.00
300+₹6.48₹1,944.00
3,000+₹5.73₹17,190.00
6,000+₹5.12₹30,720.00
9,000+₹4.83₹43,470.00

10 × ₹9.50

₹95.00

excl. GST

₹112.10 incl. 18% GST

Need volume or a scheduled delivery? Request a quote
  • Dispatch in 7–10 working days
  • GST invoice with every order
  • Standard pack: 3,000 per reel

74LVC2G14GW

₹95.00 for 10 + GST

Specifications

Input Type
Schmitt trigger
Logic Family
74LVC
Voltage - Supply
1.65V~5.5V
Propagation Delay
2.9ns@5V,50pF
Output Logic Level - Low
100mV;450mV;300mV;400mV;550mV
Features
Power shutdown protection;Noise suppression function
Operating Temperature
-40℃~+125℃
Output Logic Level - High
1.2V;1.9V;2.2V;2.3V;3.8V
Quiescent Current(Iq)
4uA
Current - Output High(IOH)
24mA
Number of Channels
2
Current - Output Low(IOL)
24mA

Packaging & compliance

RoHS
RoHS
Lifecycle
Active
Packaging
Tape & Reel (TR)
Standard pack
3,000 / Reel
Sold per
Piece
Minimum order
10 (multiples of 10)
Unit weight
0.074 g

Overview

74LVC2G14 is a dual inverter with Schmitt-trigger inputs. The inputs can be driven by 3.3 V or 5 V devices. This feature allows these devices to be used as level translators in mixed 3.3 V and 5 V environments. The device is fully specified for partial-power-down applications using IOFF. The IOFF circuit disables the outputs, preventing potentially damaging backflow current when the device is powered down.

Key features

  • Wide supply voltage range: 1.65 V to 5.5 V
  • Input overvoltage tolerance up to 5.5 V
  • High noise immunity
  • ±24 mA output drive capability (VCC = 3.0 V)
  • CMOS low power consumption
  • Latch-up performance exceeds 100 mA
  • Direct TTL-level interface compatible
  • IOFF circuit enables partial power-down mode operation
  • Unlimited rise and fall times
  • Compliant with JEDEC standards: JESD8-7 (1.65 V to 1.95 V), JESD8-5 (2.3 V to 2.7 V), JESD8C (2.7 V to 3.6 V), JESD36 (4.5 V to 5.5 V)
  • ESD protection: Human Body Model ANSI/ESDA/JEDEC JS-001 Class 3B exceeds 8000 V; Machine Model JESD22-A115C Class C exceeds 550 V; Charged Device Model ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 2000 V
  • Multiple package options

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