Nexperia

74LVC595ABQ,115

1.65V~3.6V 50mA 3.3ns@3.3V,50pF Serial-to-Serial or Parallel DHVQFN-16-EP(2.5x3.5) Shift Registers RoHS

DHVQFN-16-EP(2.5x3.5)ROHS3 CompliantActive

8-bit serial-in/serial-out or parallel-out shift register; 3-state

Manufacturer: Nexperia
Manufacturer part #: 74LVC595ABQ,115
Store part #: C458228
Package / case: DHVQFN-16-EP(2.5x3.5)
Category: Shift Registers
Packaging: Tape & Reel (TR)

Datasheet (PDF)

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8,806 in stock

#C458228

Stock & price checked 6 days ago

Quantity	Unit price	Pack price
1+	₹67.35	₹67.35
10+	₹53.01	₹530.10
30+	₹46.93	₹1,407.90
100+	₹39.33	₹3,933.00
500+	₹35.85	₹17,925.00
1,000+	₹33.90	₹33,900.00

Quantity (min 1)

1 × ₹67.35

₹67.35

excl. GST

₹79.47 incl. 18% GST

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Standard pack: 3,000 per reel

74LVC595ABQ,115

₹67.35 for 1 + GST

Specifications

Operating temperature: -40℃~+125℃
Pd - Power Dissipation: 500mW
Voltage - Supply: 1.65V~3.6V
Output Type: Tri-State
Current - Output High(IOH): 50mA
Series: 74LVC
Current - Output Low(IOL): 50mA
Output Current: 50mA
Features: Asynchronous clear function;Output enable
Propagation Delay: 3.3ns@3.3V,50pF
Function: Serial-to-Serial or Parallel

Packaging & compliance

RoHS: ROHS3 Compliant
Lifecycle: Active
ECCN: EAR99
Packaging: Tape & Reel (TR)
Standard pack: 3,000 / Reel
Sold per: Piece
Minimum order: 1
Unit weight: 0.038 g

Overview

The 74LVC595A is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset MR input. A LOW on MR will reset the shift register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the shift register is transferred to the storage register on a LOW-to-HIGH transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. Data in the storage register appears at the output whenever the output enable input (OE) is LOW. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the registers. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Applications

Serial-to-parallel data conversion
Remote control holding register

Key features

Wide supply voltage range from 1.2 V to 3.6 V
Overvoltage tolerant inputs to 5.5 V
CMOS low power dissipation
Direct interface with TTL levels
IOFF circuitry provides partial Power-down mode operation
Balanced propagation delays
All inputs have Schmitt-trigger action
Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V), JESD8-5A (2.3 V to 2.7 V), JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V; CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Specified from -40 ℃ to +85 ℃ and -40 ℃ to +125 ℃

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