74LVC8T245PW

The 74LVC8T245 and 74LVCH8T245 are 8-bit dual-supply level-shifting transceivers with 3-state outputs for bidirectional level translation. The devices feature two data input/output ports (pins An and Bn), a direction control input (DIR), an output enable input (OE), and dual supply pins VCC(A) and VCC(B). Both VCC(A) and VCC(B) can be powered at any voltage between 1.2 V and 5.5 V, making the devices suitable for level shifting between any low-voltage nodes (1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, and 5.0 V). Pins An, OE, and DIR are referenced to VCC(A), while pins Bn are referenced to VCC(B). When DIR is HIGH, data transmission from An to Bn is enabled; when DIR is LOW, data transmission from Bn to An is enabled. The output enable input (OE) can be used to disable the outputs, effectively isolating the bus. The devices are fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the outputs, preventing any damaging backflow current when the device is powered down. In power-down mode, when VCC(A) or VCC(B) is at GND level, both port A and port B are in a high-impedance off-state. The active bus-hold circuitry in the 74LVCH8T245 holds unused or floating data inputs at a valid logic level.

Key features

• Wide supply voltage range: VCC(A): 1.2 V to 5.5 V; VCC(B): 1.2 V to 5.5 V
• High noise immunity
• JEDEC compliant: JESD8-7 (1.2 V to 1.95 V), JESD8-5 (1.8 V to 2.7 V), JESD8C (2.7 V to 3.6 V), JESD36 (4.5 V to 5.5 V)
• Suspend mode
• Latch-up performance exceeds 250 mA
• ±24 mA output drive capability (VCC = 3.0 V)
• Inputs accept voltages up to 5.5 V
• Low power consumption: maximum ICC of 30 μA
• IOFF circuitry supports partial power-down mode operation
• ESD protection: HBM ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 2500 V; CDM ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 2000 V
• Multiple package options