74LVC8T595BQX

1.1V~5.5V 24mA 4.1ns@5V,50pF Serial-to-Serial or Parallel DHVQFN-20-EP(2.5x4.5) Shift Registers RoHS

DHVQFN-20-EP(2.5x4.5)ROHS3 CompliantActive

Dual supply 8-bit serial-in/serial-out or parallel-out shift register; 3-state

Manufacturer: Nexperia
Manufacturer part #: 74LVC8T595BQX
Store part #: C548860
Package / case: DHVQFN-20-EP(2.5x4.5)
Category: Shift Registers
Packaging: Tape & Reel (TR)

Datasheet (PDF)

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11,975 in stock

#C548860

Stock & price checked 6 days ago

Quantity	Unit price	Pack price
1+	₹128.58	₹128.58
10+	₹103.86	₹1,038.60
30+	₹91.29	₹2,738.70
100+	₹79.14	₹7,914.00
500+	₹71.77	₹35,885.00
1,000+	₹67.87	₹67,870.00

Quantity (min 1)

1 × ₹128.58

₹128.58

excl. GST

₹151.72 incl. 18% GST

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Standard pack: 3,000 per reel

74LVC8T595BQX

₹128.58 for 1 + GST

Specifications

Operating temperature: -40℃~+125℃
Pd - Power Dissipation: 500mW
Voltage - Supply: 1.1V~5.5V
Output Type: Tri-State
Current - Output High(IOH): 24mA
Series: 74LVC
Current - Output Low(IOL): 24mA
Output Current: 24mA
Features: Asynchronous clear function;Output enable
Propagation Delay: 4.1ns@5V,50pF
Function: Serial-to-Serial or Parallel

Packaging & compliance

RoHS: ROHS3 Compliant
Lifecycle: Active
ECCN: EAR99
Packaging: Tape & Reel (TR)
Standard pack: 3,000 / Reel
Sold per: Piece
Minimum order: 1
Unit weight: 0.075 g

Overview

The 74LVC8T595 is an 8-bit serial-in, serial-or-parallel-out shift register with storage register and 3-state outputs. The shift register and storage register have separate clocks. Data is shifted on the rising edge of the SHCP input. On the rising edge of the STCP input, the data in the shift register is transferred to the storage register. If the two clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. VCC(A) and VCC(B) can be powered at any voltage between 1.1V and 5.5V, making the device suitable for translation between any voltage nodes (1.2V, 1.5V, 1.8V, 2.5V, 3.3V, and 5.0V). Pins MR̄, SHCP, STCP, OE̅, DS, and Q7S are referenced to VCC(A), and pins Qn are referenced to VCC(B). The device is fully specified for partial power-down applications using IOFF. The IOFF circuit disables the outputs, preventing any damaging backflow current through the device when it is powered down. In standby mode, when VCC(A) is at ground level, the Qn outputs are in a high-impedance off state.

Key features

Wide supply voltage range: VCC(A): 1.1V to 5.5V; VCC(B): 1.1V to 5.5V
High noise immunity
Standby mode
Latch-up performance exceeds 100mA per JESD 78 Class II
±24mA output drive (VCC(A)=VCC(B)=3.0V)
Inputs accept voltages up to 5.5V
IOFF circuitry supports partial power-down mode operation
JEDEC standards compliant: JESD8-12A (1.1V to 1.3V), JESD8-11A (1.4V to 1.6V), JESD8-7 (1.65V to 1.95V), JESD8-5 (2.3V to 2.7V), JESD8C (3.0V to 3.6V), JESD12-6 (4.5V to 5.5V)
ESD protection: HBM: exceeds 4000V per ANSI/ESDA/JEDEC JS-001 Class 3A; CDM: exceeds 1000V per ANSI/ESDA/JEDEC JS-002 Class C3
Operating temperature range: -40°C to +85°C and -40°C to +125°C

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