CD40109BNSR

This is a CMOS quad low-to-high voltage level translator, high-voltage type, rated at 20V. The CD40109 contains four low-to-high voltage level translation circuits. Each circuit translates a low-voltage digital logic input signal (A, B, C, D) — where logic 1 = VCC and logic 0 = VSS — to a higher-voltage output signal (E, F, G, H) where logic 1 = VDD and logic 0 = VSS. Unlike other low-to-high level translation circuits, the CD40109 does not require the high-voltage supply (VDD) to be applied before the low-voltage supply (VCC) or input signals; there are no restrictions on the power-up sequence of VDD, VCC, or input signals. Furthermore, with one special exception, there are no restrictions on the relative magnitudes of supply voltages or input signals within the device's maximum ratings, as long as the input signal swing is between VSS and at least 0.7VCC: VCC may exceed VDD, and input signals may exceed both VCC and VDD. When operating in VCC > VDD mode, the CD40109 functions as a high-to-low level translator. The CD40109 features individual three-state outputs; when any individual active-low three-state output enable pin is driven low, the corresponding output enters a high-impedance state. The CD40109B series is available in multiple package options: 16-pin ceramic DIP (suffix F3A), 16-pin plastic DIP (suffix E), 16-pin small-outline package (suffix NSR), and 16-pin thin shrink small-outline package (suffixes PW and PWR).

Applications

• High-or-low fevel-shifting with thrse-state outputs for unidirectional or bidirectional bussing
• Isolation of logic subsystems using separ ate power supplies from supply soquenc. ing. supply loss and supply regulation considerations
• Independence of power supply sequence considerations-- Vcc can oxceed VpD. input signals can exceed both Vcc and VDD
• Up and down level-shifting capability
• Three-state outputs with seperate enable controls
• Standardized, sy mmetrical output characteristics
• 100% testad for quiescent current at 20 V
• Maximum input current of μA at 18 V over full package-temperature range; 100 nA at 18 V and
• Noise margin (fufl package-temperature range) = 1 V at Vcc = 5 v, Vdd = 10 v = 2 V at Vcc = 10 v, Vdd = 15 v
• 5-V, 10-V, and 15-V parametric ratings
• Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Speclflcations for Description of 'B' Serles CMOs Devices"

Key features

• High-Voltage Types (20-Volt Rating)
• Does not require the presence of the high-voltage supply (VDD) before the application of either the low-voltage supply (VCC) or the input signals. No restrictions on the sequence of application of VDD, VCC, or the input signals.
• With one exception, no restrictions on the relative magnitudes of the supply voltages or input signals within the device maximum ratings, provided that the input signal swings between VSS and at least 0.7VCC; VCC may exceed VDD, and input signals may exceed VCC and VDD. When operated in the mode VCC > VDD, it will operate as a high-to-low level-shifter.
• Features individual three state output capability. A low level on any of the separately enabled three-state output controls produces a high-impedance state in the corresponding output.
• The CD40109B-Series types are supplied in 16-lead ceramic dual-in-line packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).