Varnitronics
CD4043BDR TI
TI

CD4043BDR

SR Latch 3V~18V 4 50ns SOIC-16 Latches RoHS

SOIC-16ROHS3 CompliantActive

CMOS Quad 3-State R/S Latches

Manufacturer
TI
Manufacturer part #
CD4043BDR
Store part #
C40131
Package / case
SOIC-16
Category
Latches
Packaging
Tape & Reel (TR)
Datasheet (PDF)

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100% Authentic · 30-Day Return or Replacement · policy

2,048 in stock

#C40131

Stock & price checked 5 days ago

QuantityUnit pricePack price
1+₹69.05₹69.05
10+₹58.40₹584.00
30+₹51.03₹1,530.90
100+₹44.73₹4,473.00
500+₹42.77₹21,385.00
1,000+₹41.69₹41,690.00

1 × ₹69.05

₹69.05

excl. GST

₹81.48 incl. 18% GST

Need volume or a scheduled delivery? Request a quote
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  • GST invoice with every order
  • Standard pack: 2,500 per reel

CD4043BDR

₹69.05 for 1 + GST

Specifications

Series
CD40
Logic Type
SR Latch
Quiescent Current
20uA
Voltage - Supply
3V~18V
Output Type
Tri-State
Current - Output Low(IOL)
4.2mA
Operating Temperature
-55℃~+125℃
Current - Output High(IOH)
4.2mA
Number of Gates
4
Propagation Delay
50ns

Packaging & compliance

RoHS
ROHS3 Compliant
Lifecycle
Active
ECCN
EAR99
Packaging
Tape & Reel (TR)
Standard pack
2,500 / Reel
Sold per
Piece
Minimum order
1
Unit weight
0.296 g

Overview

CD4043B types are quad crosscoupled 3-state CMOS NOR latches and the CD4044B types are quad cross-coupled 3-state CMOS NAND latches. Each latch has a separate Q output and individual SET and RESET inputs. The Q outputs are controlled by a common ENABLE input. A logic "1" or high on the ENABLE input connects the latch.states to the Q outputs. A logic "0" or low on the ENABLE input disconnects the latch states from the Q outputs, resulting in an open circuit condition on the Q outputs. The open circuit feature allows common busing of the outputs.

Applications

  • Hold registers in multi-register systems
  • 4-bit independent storage with output enable
  • Strobed registers
  • General-purpose digital logic
  • CD4043B for positive-logic systems
  • CD4044B for negative-logic systems

Key features

  • 3-state outputs with common output ENABLE
  • Separate SET and RESET inputs for each latch
  • NOR and NAND configurations
  • 5-V, 10-V, and 15-V parametric ratings
  • Standardized symmetrical output characteristics
  • 100% tested for quiescent current at μ20νν
  • Maximum input current of μμ at 78ν over full package temperature range; 100 nA at 18 V and z5℃
  • Noise margin (over full package temperature range): 1 V at ΔDD = 5V, 2V at VDD = 10V, 2.5νV at vDD = 15V
  • Meets all requirements of JEDEC Tentative Standard No. 1aB, "Standard Specifications for Description of B′ Series CMOS Devices"
  • Holding register in multi-register system
  • Four bits of independent storage with output ENABLE
  • Strobed register
  • General digital logic
  • CD4643B for positive logic systems
  • CD4044B for negative logic systems

Alternatives

Similar parts — check the datasheet before substituting.

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