
CD4044BDR
SR Latch 3V~18V 4 50ns SOIC-16 Latches RoHS
CMOS Quad 3-State R/S Latches
Every Order Guarantee
100% Authentic · 30-Day Return or Replacement · policy
3,905 in stock
#C133986
Stock & price checked 6 days ago
| Quantity | Unit price | Pack price |
|---|---|---|
| 1+ | ₹71.42 | ₹71.42 |
| 10+ | ₹57.86 | ₹578.60 |
| 30+ | ₹50.99 | ₹1,529.70 |
| 100+ | ₹44.12 | ₹4,412.00 |
| 500+ | ₹40.14 | ₹20,070.00 |
| 1,000+ | ₹33.81 | ₹33,810.00 |
1 × ₹71.42
₹71.42
excl. GST
₹84.28 incl. 18% GST
- Dispatch in 7–10 working days
- GST invoice with every order
- Standard pack: 2,500 per reel
CD4044BDR
₹71.42 for 1 + GST
Specifications
- Series
- CD40
- Logic Type
- SR Latch
- Quiescent Current
- 0.02uA
- Voltage - Supply
- 3V~18V
- Output Type
- Tri-State
- Current - Output Low(IOL)
- 4.2mA
- Operating Temperature
- -55℃~+125℃
- Current - Output High(IOH)
- 4.2mA
- Number of Gates
- 4
- Propagation Delay
- 50ns
Packaging & compliance
- RoHS
- ROHS Compliant
- Lifecycle
- Active
- ECCN
- EAR99
- Packaging
- Tape & Reel (TR)
- Standard pack
- 2,500 / Reel
- Sold per
- Piece
- Minimum order
- 1
- Unit weight
- 0.296 g
Overview
CD4043B types are quad crosscoupled 3-state CMOS NOR latches and the CD4044B types are quad cross-coupled 3-state CMOS NAND latches. Each latch has a separate Q output and individual SET and RESET inputs. The Q outputs are controlled by a common ENABLE input. A logic "1" or high on the ENABLE input connects the latch.states to the Q outputs. A logic "0" or low on the ENABLE input disconnects the latch states from the Q outputs, resulting in an open circuit condition on the Q outputs. The open circuit feature allows common busing of the outputs.
Applications
- Hold registers in multi-register systems
- 4-bit independent storage with output enable
- Strobed registers
- General-purpose digital logic
- CD4043B for positive-logic systems
- CD4044B for negative-logic systems
Key features
- 3-state outputs with common output ENABLE
- Separate SET and RESET inputs for each latch
- NOR and NAND configurations
- 5-V, 10-V, and 15-V parametric ratings
- Standardized symmetrical output characteristics
- 100% tested for quiescent current at μ20νν
- Maximum input current of μμ at 78ν over full package temperature range; 100 nA at 18 V and z5℃
- Noise margin (over full package temperature range): 1 V at ΔDD = 5V, 2V at VDD = 10V, 2.5νV at vDD = 15V
- Meets all requirements of JEDEC Tentative Standard No. 1aB, "Standard Specifications for Description of B′ Series CMOS Devices"
- Holding register in multi-register system
- Four bits of independent storage with output ENABLE
- Strobed register
- General digital logic
- CD4643B for positive logic systems
- CD4044B for negative logic systems
Alternatives
Similar parts — check the datasheet before substituting.
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