Varnitronics
CD4094BM-TD TDSEMIC
TDSEMIC

CD4094BM-TD

3V~15V 3.6mA 95ns@15V,50pF Serial-to-Parallel SOP-16 Shift Registers RoHS

SOP-16ROHS CompliantActive

8-bit shift register with three-state output

Manufacturer
TDSEMIC
Manufacturer part #
CD4094BM-TD
Store part #
C42421855
Package / case
SOP-16
Packaging
Tape & Reel (TR)
Datasheet (PDF)

Every Order Guarantee

100% Authentic · 30-Day Return or Replacement · policy

2,195 in stock

#C42421855

Stock & price checked 5 days ago

QuantityUnit pricePack price
5+₹20.60₹103.00
50+₹16.47₹823.50
150+₹14.42₹2,163.00
500+₹12.87₹6,435.00
2,500+₹10.72₹26,800.00
5,000+₹10.09₹50,450.00

5 × ₹20.60

₹103.00

excl. GST

₹121.54 incl. 18% GST

Need volume or a scheduled delivery? Request a quote
  • Dispatch in 7–10 working days
  • GST invoice with every order
  • Standard pack: 2,500 per reel

CD4094BM-TD

₹103.00 for 5 + GST

Specifications

Operating temperature
-40℃~+85℃
Pd - Power Dissipation
500mW
Voltage - Supply
3V~15V
Output Type
Tri-State
Current - Output High(IOH)
8.8mA
Current - Output Low(IOL)
8.8mA
Output Current
3.6mA
Features
Output enable
Propagation Delay
95ns@15V,50pF
Function
Serial-to-Parallel

Packaging & compliance

RoHS
ROHS Compliant
Lifecycle
Active
Packaging
Tape & Reel (TR)
Standard pack
2,500 / Reel
Sold per
Piece
Minimum order
5 (multiples of 5)
Unit weight
0.274 g

Overview

The CD4094B is a CMOS IC consisting of an 8-bit serial shift register and a 3-state output buffer. The register features a storage latch function; the IC uses the STROBE signal to determine whether the latches receive data from each bit of the shift register and whether data is transferred from the latches to the 3-state output buffer. When STROBE is 0, the latched input data reflects the output of each bit of the shift register. When STROBE is 1, data is transferred through the latches to the 3-state output buffer. When OUTPUTENABLE is 1, data is transferred to the output buffer and converted to parallel form.

Key features

  • Supply voltage range: 5.0V - 18V
  • High noise margin: 45% of VDD (typical)
  • Output levels and drive current meet TTL interface requirements (VDD = 5V)
  • Three-state output bus signal
  • Package types: DIP-16, SOP-16, TSSOP-16

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