CDCM9102RHBR

The CDCM9102 is a low-jitter clock generator designed to provide reference clocks for communication standards such as PCI Express. This device supports up to PCIe Gen 3 and is easy to configure and use. The CDCM9102 provides two 100 MHz differential clock ports. The output types supported by these ports include LVPECL, LVDS, or a pair of LVCMOS buffers. HCSL signal transmission is supported by an AC coupling network. Users can configure the type of output buffer required for the bundled device pins. In addition, a single-ended 25 MHz clock output port is provided. The uses of this port include general timing, timing Ethernet physical layer (PHY), or providing a reference clock for additional clock generators. All generated clocks are derived from a single external 25 MHz crystal.

Applications

• PCIe Gen 1, Gen 2, and Gen 3 reference clock generation
• General-purpose timing

Key features

• Integrated low-noise clock generator with PLL, VCO, and loop filter
• Two low-noise 100MHz clock outputs (LVPECL, LVDS, or LVCMOS pairs)
• HCSL signaling level support (AC-coupled)
• Typical period jitter: 21ps pk-pk
• Typical random jitter: 510ps RMS
• Pin-selectable output type
• Additional single-ended 25MHz output
• Integrated crystal input accepting 25MHz crystal
• Output enable pin for device and output shutdown
• 32-pin 5mm×5mm VQFN package
• ESD protection exceeding 2000V HBM and 500V CDM
• Industrial temperature range (−40°C to 85°C)
• 3.3V supply