EnergyMath

EM74LVC08AD

Schmitt trigger 1.65V~5.5V 5.5ns@5.5V,15pF 10uA SOP-14L Gates and Inverters

SOP-14LRoHSActive

Quad 2-input AND gate

Manufacturer: EnergyMath
Manufacturer part #: EM74LVC08AD
Store part #: C49188174
Package / case: SOP-14L
Category: Gates and Inverters
Packaging: Tape & Reel (TR)

Datasheet (PDF)

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1,455 in stock

#C49188174

Stock & price checked 6 days ago

Quantity	Unit price	Pack price
5+	₹14.62	₹73.10
50+	₹11.56	₹578.00
150+	₹10.03	₹1,504.50
500+	₹8.88	₹4,440.00
3,000+	₹7.96	₹23,880.00
6,000+	₹7.50	₹45,000.00

Quantity (min 5, multiples of 5)

5 × ₹14.62

₹73.10

excl. GST

₹86.26 incl. 18% GST

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Standard pack: 3,000 per reel

EM74LVC08AD

₹73.10 for 5 + GST

Specifications

Input Type: Schmitt trigger
Logic Family: 74LVC
Voltage - Supply: 1.65V~5.5V
Output Logic Level - Low: 100mV;450mV;300mV;400mV;550mV
Propagation Delay: 5.5ns@5.5V,15pF
Input Logic Level - Low: 120mV;700mV;800mV
Input Logic Level - High: 1.08V;1.7V;2V
Features: Local shutdown mode;Overvoltage-tolerant input
Operating Temperature: -40℃~+125℃
Output Logic Level - High: 1.2V;1.9V;2.2V;2.4V;3.8V
Quiescent Current(Iq): 10uA
Current - Output High(IOH): 32mA
Number of Channels: 4;2
Current - Output Low(IOL): 32mA

Packaging & compliance

RoHS: RoHS
Lifecycle: Active
Packaging: Tape & Reel (TR)
Standard pack: 3,000 / Reel
Sold per: Piece
Minimum order: 5 (multiples of 5)
Unit weight: 0.273 g

Overview

This device is a quad 2-input AND gate whose inputs can be driven by 3.3V or 5V devices, making it suitable for use as a level translator in mixed 3.3V/5V applications. Schmitt-trigger action on all inputs makes the circuit tolerant of slower input rise and fall times. The device is fully specified for partial-power-down applications using I_OFF; the I_OFF circuit disables the outputs, preventing potentially damaging backflow current from passing through the device when it is powered down.

Key features

Wide supply voltage range: 1.2 V ~ 5.5 V
Input overvoltage tolerance up to 5.5 V
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct TTL-level interface compatible
I_OFF circuit for partial power-down mode operation
JEDEC compliant: JESD8-7 (1.65 V to 1.95 V), JESD8-5 (2.3 V to 2.7 V), JESD8C (2.7 V to 3.6 V), JESD36 (4.5 V to 5.5 V)
ESD protection: HBM ANSI/ESDA/JEDEC JS-001 Class 3A exceeds 6000 V; CDM ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 2000 V
Multiple package options

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