Varnitronics
EM74LVC1G00GM EnergyMath
EnergyMath

EM74LVC1G00GM

Schmitt trigger 1.65V~5.5V 3.8ns@5.5V,50pF 4uA DFN-6(1x1.5) Gates and Inverters

DFN-6(1x1.5)RoHSActive

Single 2-input NAND gate

Manufacturer
EnergyMath
Manufacturer part #
EM74LVC1G00GM
Store part #
C49188164
Package / case
DFN-6(1x1.5)
Packaging
Tape & Reel (TR)
Datasheet (PDF)

Every Order Guarantee

100% Authentic · 30-Day Return or Replacement · policy

2,980 in stock

#C49188164

Stock & price checked 26 h ago

QuantityUnit pricePack price
5+₹14.57₹72.85
50+₹11.52₹576.00
150+₹9.99₹1,498.50
500+₹8.85₹4,425.00
3,000+₹7.94₹23,820.00
6,000+₹7.47₹44,820.00

5 × ₹14.57

₹72.85

excl. GST

₹85.96 incl. 18% GST

Need volume or a scheduled delivery? Request a quote
  • Dispatch in 7–10 working days
  • GST invoice with every order
  • Standard pack: 3,000 per reel

EM74LVC1G00GM

₹72.85 for 5 + GST

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Specifications

Input Type
Schmitt trigger
Logic Family
74LVC
Voltage - Supply
1.65V~5.5V
Propagation Delay
3.8ns@5.5V,50pF
Input Logic Level - Low
700mV;800mV
Input Logic Level - High
1.7V;2V
Features
Overvoltage-tolerant input;Local shutdown mode
Operating Temperature
-40℃~+125℃
Quiescent Current(Iq)
4uA
Current - Output High(IOH)
24mA
Number of Channels
1;2
Current - Output Low(IOL)
24mA

Packaging & compliance

RoHS
RoHS
Lifecycle
Active
Moisture sensitivity
MSL 1 (unlimited)
Packaging
Tape & Reel (TR)
Standard pack
3,000 / Reel
Sold per
Piece
Minimum order
5 (multiples of 5)
Unit weight
0.026 g

Overview

The EM74LVC1G00 is a single 2-input NAND gate. Its inputs can be driven by 3.3V or 5V devices. This feature allows the device to be used as a level translator in mixed 3.3V and 5V environments. Schmitt-trigger action on all inputs enables the circuit to tolerate slower input rise and fall times. The device is fully specified for partial-power-down applications using IOFF. The IOFF circuit disables the outputs, preventing potentially destructive backflow current when the device is powered down.

Key features

  • Wide supply voltage range: 1.65V~5.5V
  • Input overvoltage tolerance up to 5.5V
  • High noise immunity
  • CMOS low power consumption
  • IOFF circuitry for partial power-down mode operation
  • ±24mA output drive capability (VCC=3.0V)
  • Latch-up performance exceeds 100mA
  • Direct TTL-level interface compatible
  • Compliant with JEDEC standards: JESD8-7 (1.65V~1.95V), JESD8-5 (2.3V~2.7V), JESD8C (2.7V~3.6V), JESD36 (4.5V~5.5V)
  • ESD protection: HBM ANSI/ESDA/JEDEC JS-001 Class 3B exceeds 8000V; MM JESD22-A115C Class C exceeds 550V; CDM ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 2000V
  • Multiple package options

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