Varnitronics
EM74LVC1G02GM EnergyMath
EnergyMath

EM74LVC1G02GM

Schmitt trigger 1.65V~5.5V 3.8ns@5.5V,50pF 4uA DFN-6(1x1.5) Gates and Inverters

DFN-6(1x1.5)RoHSActive

Single 2-input NOR gate

Manufacturer
EnergyMath
Manufacturer part #
EM74LVC1G02GM
Store part #
C49188160
Package / case
DFN-6(1x1.5)
Packaging
Tape & Reel (TR)
Datasheet (PDF)

Every Order Guarantee

100% Authentic · 30-Day Return or Replacement · policy

2,990 in stock

#C49188160

Stock & price checked 6 days ago

QuantityUnit pricePack price
5+₹14.57₹72.85
50+₹11.52₹576.00
150+₹9.99₹1,498.50
500+₹8.85₹4,425.00
3,000+₹7.94₹23,820.00
6,000+₹7.47₹44,820.00

5 × ₹14.57

₹72.85

excl. GST

₹85.96 incl. 18% GST

Need volume or a scheduled delivery? Request a quote
  • Dispatch in 7–10 working days
  • GST invoice with every order
  • Standard pack: 3,000 per reel

EM74LVC1G02GM

₹72.85 for 5 + GST

Specifications

Input Type
Schmitt trigger
Logic Family
74LVC
Voltage - Supply
1.65V~5.5V
Propagation Delay
3.8ns@5.5V,50pF
Output Logic Level - Low
800mV
Features
Local shutdown mode;Overvoltage-tolerant input
Input Logic Level - Low
700mV;800mV
Operating Temperature
-40℃~+125℃
Input Logic Level - High
1.7V;2V
Quiescent Current(Iq)
4uA
Current - Output High(IOH)
24mA
Number of Channels
1;2
Current - Output Low(IOL)
24mA

Packaging & compliance

RoHS
RoHS
Lifecycle
Active
Packaging
Tape & Reel (TR)
Standard pack
3,000 / Reel
Sold per
Piece
Minimum order
5 (multiples of 5)
Unit weight
0.027 g

Overview

The EM74LVC1G02 is a single 2-input NOR gate. Its inputs can be driven by 3.3V or 5V devices. This feature allows these devices to be used as level translators in mixed 3.3V and 5V environments. Schmitt-trigger action on all inputs makes the circuit tolerant of slower input rise and fall times. The device is fully specified for partial power-down applications using IOFF. The IOFF circuit disables the outputs, preventing potentially damaging reverse current flow through the device when it is powered down.

Key features

  • Wide supply voltage range: 1.65 V to 5.5 V
  • Overvoltage-tolerant inputs up to 5.5 V
  • High noise immunity
  • CMOS low power consumption
  • IOFF circuitry supports partial power-down mode operation
  • Output drive capability ±24 mA (VCC = 3.0 V)
  • Latch-up performance exceeds 100 mA
  • Direct TTL-level interface
  • JEDEC compliant: JESD8-7 (1.65 V to 1.95 V), JESD8-5 (2.3 V to 2.7 V), JESD8C (2.7 V to 3.6 V), JESD36 (4.5 V to 5.5 V)
  • ESD protection: HBM ANSI/ESDA/JEDEC JS-001 Class 3B exceeds 8000 V, MM JESD22-A115C Class C exceeds 550 V, CDM ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 2000 V
  • Multiple package options

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