Varnitronics
EM74LVC2G06GW EnergyMath
EnergyMath

EM74LVC2G06GW

Schmitt trigger 1.65V~5.5V 3ns@5.5V,50pF 4uA 2 SOT-363 Gates and Inverters

SOT-363RoHSActive

Inverters with open-drain outputs

Manufacturer
EnergyMath
Manufacturer part #
EM74LVC2G06GW
Store part #
C49188103
Package / case
SOT-363
Packaging
Tape & Reel (TR)
Datasheet (PDF)

Every Order Guarantee

100% Authentic · 30-Day Return or Replacement · policy

2,980 in stock

#C49188103

Stock & price checked 5 days ago

QuantityUnit pricePack price
10+₹7.55₹75.50
100+₹5.98₹598.00
300+₹5.19₹1,557.00
3,000+₹4.59₹13,770.00
6,000+₹4.11₹24,660.00
9,000+₹3.88₹34,920.00

10 × ₹7.55

₹75.50

excl. GST

₹89.09 incl. 18% GST

Need volume or a scheduled delivery? Request a quote
  • Dispatch in 7–10 working days
  • GST invoice with every order
  • Standard pack: 3,000 per reel

EM74LVC2G06GW

₹75.50 for 10 + GST

Specifications

output type
Open-drain
Logic Family
74LVC
Input Type
Schmitt trigger
Voltage - Supply
1.65V~5.5V
Output Logic Level - Low
800mV
Propagation Delay
3ns@5.5V,50pF
Features
Power shutdown protection;Noise suppression function
Operating Temperature
-40℃~+125℃
Quiescent Current(Iq)
4uA
Number of Channels
2
Current - Output Low(IOL)
24mA

Packaging & compliance

RoHS
RoHS
Lifecycle
Active
Packaging
Tape & Reel (TR)
Standard pack
3,000 / Reel
Sold per
Piece
Minimum order
10 (multiples of 10)
Unit weight
0.033 g

Overview

The EM74LVC2G06 is a dual inverter with open-drain outputs. Its inputs can be driven by 3.3 V or 5 V devices. This feature allows the device to be used as a level translator in mixed 3.3 V and 5 V environments. Schmitt-trigger action on all inputs makes the circuit tolerant of slower input rise and fall times. The device is fully specified for partial power-down applications using I<sub>OFF</sub>. The I<sub>OFF</sub> circuit disables the outputs, preventing potentially destructive backflow current when the device is powered down.

Key features

  • Wide supply voltage range: 1.65 V to 5.5 V
  • Input overvoltage tolerance up to 5.5 V
  • High noise immunity
  • Low-power CMOS
  • IOFF circuitry for partial power-down operation
  • 24 mA output drive capability (VCC = 3.0 V)
  • Latch-up performance exceeds 100 mA
  • Direct interface with TTL levels
  • JEDEC compliant: JESD8-7 (1.65 V to 1.95 V), JESD8-5 (2.3 V to 2.7 V), JESD8C (2.7 V to 3.6 V), JESD36 (4.5 V to 5.5 V)
  • ESD protection: Human Body Model per ANSI/ESDA/JEDEC JS-001 Class 3B, exceeds 8000 V; Machine Model per JESD22-A115C Class C, exceeds 550 V; Charged Device Model per ANSI/ESDA/JEDEC JS-002 Class C3, exceeds 2000 V
  • Multiple package options

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