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SN74LVC1G08DCKR1.65V~5.5V 3.6ns@3.3V 10uA SC-70-5 Gates and Inverters RoHS
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EnergyMathDatasheet (PDF)
EM74LVC32APW
Schmitt trigger 1.65V~5.5V 5.5ns@5.5V,15pF 40uA TSSOP-14L Gates and Inverters
TSSOP-14LRoHSActive
Quad 2-input OR gate
- Manufacturer
- EnergyMath
- Manufacturer part #
- EM74LVC32APW
- Store part #
- C49188086
- Package / case
- TSSOP-14L
- Category
- Gates and Inverters
- Packaging
- Tape & Reel (TR)
Every Order Guarantee
100% Authentic · 30-Day Return or Replacement · policy
1,745 in stock
#C49188086
Stock & price checked 42 h ago
| Quantity | Unit price | Pack price |
|---|---|---|
| 5+ | ₹20.70 | ₹103.50 |
| 50+ | ₹16.26 | ₹813.00 |
| 150+ | ₹14.35 | ₹2,152.50 |
| 500+ | ₹11.97 | ₹5,985.00 |
| 3,000+ | ₹10.91 | ₹32,730.00 |
| 6,000+ | ₹10.28 | ₹61,680.00 |
5 × ₹20.70
₹103.50
excl. GST
₹122.13 incl. 18% GST
- Dispatch in 7–10 working days
- GST invoice with every order
- Standard pack: 3,000 per reel
EM74LVC32APW
₹103.50 for 5 + GST
Specifications
- Input Type
- Schmitt trigger
- Logic Family
- 74LVC
- Voltage - Supply
- 1.65V~5.5V
- Propagation Delay
- 5.5ns@5.5V,15pF
- Output Logic Level - Low
- 100mV;450mV;300mV;400mV;550mV
- Features
- Local shutdown mode;Overvoltage-tolerant input
- Input Logic Level - Low
- 120mV;700mV;800mV
- Operating Temperature
- -40℃~+125℃
- Input Logic Level - High
- 1.08V;1.7V;2V
- Output Logic Level - High
- 1.2V;1.9V;2.2V;2.4V;3.8V
- Quiescent Current(Iq)
- 40uA
- Current - Output High(IOH)
- 32mA
- Number of Channels
- 4;2
- Current - Output Low(IOL)
- 32mA
Packaging & compliance
- RoHS
- RoHS
- Lifecycle
- Active
- Moisture sensitivity
- MSL 3 (168 hours)
- Packaging
- Tape & Reel (TR)
- Standard pack
- 3,000 / Reel
- Sold per
- Piece
- Minimum order
- 5 (multiples of 5)
- Unit weight
- 0.225 g
Overview
The EM74LVC32A is a quad 2-input OR gate. Its inputs can be driven by 3.3V or 5V devices. This feature allows the device to be used as a level translator in mixed 3.3V and 5V environments. All inputs feature Schmitt-trigger action, enabling the circuit to tolerate slower input rise and fall times. The device fully supports partial power-down applications using the IOFF circuit. The IOFF circuit disables the outputs, preventing potentially destructive backflow currents when the device is powered down.
Key features
- Wide supply voltage range: 1.2 V ~ 5.5 V
- Input overvoltage tolerance up to 5.5 V
- CMOS low power consumption
- I<sub>OFF</sub> circuitry for partial power-down mode operation
- Latch-up performance exceeds 250 mA
- Direct TTL-level interface compatible
- JEDEC standards compliant: JESD8-7A (1.65 V to 1.95 V), JESD8-5A (2.3 V to 2.7 V), JESD8-C (2.7 V to 3.6 V), JESD36 (4.5 V to 5.5 V)
- ESD protection: HBM ANSI/ESDA/JEDEC JS-001 Class 3A exceeds 6000 V; CDM ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 2000 V
- Multiple package options
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