EnergyMath

EM74LVC86APW

Schmitt trigger 1.65V~5.5V 5.5ns@5.5V,15pF 40uA TSSOP-14L Gates and Inverters

TSSOP-14LRoHSActive

Quad 2-input EXCLUSIVE gate

Manufacturer: EnergyMath
Manufacturer part #: EM74LVC86APW
Store part #: C49188084
Package / case: TSSOP-14L
Category: Gates and Inverters
Packaging: Tape & Reel (TR)

Datasheet (PDF)

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2,740 in stock

#C49188084

Stock & price checked 5 days ago

Quantity	Unit price	Pack price
5+	₹14.59	₹72.95
50+	₹12.74	₹637.00
150+	₹11.95	₹1,792.50
500+	₹10.95	₹5,475.00
3,000+	₹10.52	₹31,560.00
6,000+	₹10.25	₹61,500.00

Quantity (min 5, multiples of 5)

5 × ₹14.59

₹72.95

excl. GST

₹86.08 incl. 18% GST

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Standard pack: 3,000 per reel

EM74LVC86APW

₹72.95 for 5 + GST

Specifications

Input Type: Schmitt trigger
Logic Family: 74LVC
Voltage - Supply: 1.65V~5.5V
Propagation Delay: 5.5ns@5.5V,15pF
Output Logic Level - Low: 450mV;300mV;400mV;550mV
Features: Local shutdown mode;Overvoltage-tolerant input
Input Logic Level - Low: 120mV;700mV;800mV
Operating Temperature: -40℃~+125℃
Input Logic Level - High: 1.08V;1.7V;2V
Output Logic Level - High: 1.2V;1.9V;2.2V;2.4V;3.8V
Quiescent Current(Iq): 40uA
Current - Output High(IOH): 32mA
Number of Channels: 4;2
Current - Output Low(IOL): 32mA

Packaging & compliance

RoHS: RoHS
Lifecycle: Active
Packaging: Tape & Reel (TR)
Standard pack: 3,000 / Reel
Sold per: Piece
Minimum order: 5 (multiples of 5)
Unit weight: 0.185 g

Overview

EM74LVC86A is a quad 2-input exclusive-OR gate. Its inputs can be driven by 3.3V or 5V devices. This feature allows the device to be used as a level translator in mixed 3.3V and 5V applications. Schmitt-trigger action on all inputs makes the circuit tolerant to slower input rise and fall times. The device is fully specified for partial power-down applications using I_OFF. The I_OFF circuitry disables the outputs, preventing damaging reverse current flow through the device when it is powered down.

Key features

Wide supply voltage range: 1.2V ~ 5.5V
Input overvoltage tolerance up to 5.5V
CMOS low power consumption
Latch-up performance exceeds 100mA
Direct TTL-level interface compatible
I_OFF circuit enables partial power-down mode operation
JEDEC compliant: JESD8-7 (1.65V ~ 1.95V), JESD8-5 (2.3V ~ 2.7V), JESD8C (2.7V ~ 3.6V), JESD36 (4.5V ~ 5.5V)
ESD protection: HBM ANSI/ESDA/JEDEC JS-001 Class 3A exceeds 6000V; CDM ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 2000V
Multiple package options

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