GD25Q127CSIGR

The GD25Q127C (128M-bit) Serial flash supports the standard Serial Peripheral Interface (SPI), and supports the Dual/Quad SPI: Serial Clock, Chip Select, Serial Data I/O0 (SI), I/O1 (SO), I/O2 (WP#), and I/O3 (HOLD#/ RESET#). The Dual I/O data is transferred with speed of 208Mbits/s and the Quad I/O & Quad output data is transferred with speed of 416Mbits/s.

Key features

• 128M-bit Serial Flash
• 16384K-byte
• 256 bytes per programmable page
• Fast Program/Erase Speed
• Page Program time: 0.5ms typical
• Sector Erase time: 50ms typical
• Block Erase time: 0.16/0.3s typical
• Chip Erase time: 50s typical
• Standard, Dual, Quad SPI
• Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD#/ RESET#
• Dual SPI: SCLK, CS#, IO0, IO1, WP#, HOLD#/ RESET#
• Quad SPI: SCLK, CS#, IO0, IO1, IO2, IO3
• Flexible Architecture
• Uniform Sector of 4K-byte
• Uniform Block of 32/64K-byte
• High Speed Clock Frequency
• 104MHz for Standard and Dual SPI fast read with 30PF load
• Dual I/O Data transfer up to 208Mbits/s
• Quad I/O Data transfer up to 416Mbits/s
• Low Power Consumption
• 20μA typical standby current
• 1μA typical power down current
• Software/Hardware Write Protection
• Write protect all/portion of memory via software
• Enable/Disable protection with WP# Pin
• Top/Bottom Block protection
• Advanced Security Features
• 128-bit Unique ID for each device
• 3x1024-Byte Security Registers With OTP Locks
• Discoverable parameters (SFDP) register
• Allows XIP (execute in place) Operation
• Continuous Read With 8/16/32/64-byte Wrap
• Single Power Supply Voltage
• Full voltage range: 2.7~3.6V
• Minimum 100,000 Program/Erase Cycles
• Data Retention
• 20-year data retention typical
• Package Information
• SOP8 (208mil)
• VSOP8 (208mil)
• SOP16 (300mil)
• DIP8 (300mil)
• WSON8 (8*6mm)
• WSON8 (6*5mm)
• TFBGA-24 [6*4 ball array]