HEF4094BT,653-JSM

The 4094 is an 8-stage serial shift register. It features a storage latch for each stage, used to strobe data from the serial input to the parallel-buffered three-state outputs QP0 through QP7. The parallel outputs can be connected directly to a common bus. Data is shifted on the rising edge of the clock. When the Strobe (STR) input is high, data from each shift register stage is transferred to the storage register. As long as the Output Enable (OE) signal is high, the data in the storage register appears at the outputs. Two serial outputs (QS1 and QS2) are available for cascading multiple 4094 devices. On the rising edge of the clock, QS1 captures serial data to enable high-speed operation in cascaded systems with fast clock rise times. On the next falling edge of the clock, QS2 captures the same serial data. This can be used to cascade 4094 devices when clock rise times are slow. It operates within the recommended ΔVDD supply voltage range (relative to VSS, typically ground) of 3V to 15V. Unused inputs must be connected to ΔVDD, VSS, or other inputs.

Key features

• Wide supply voltage range: 3V to 15V
• Fully static operation
• Parametric ratings at 5V, 10V, and 15V
• Standardized symmetrical output characteristics
• Operating temperature range: -40℃ to +125℃
• Package: SOP16