HG25Q256BMW/TR

HG25Q256B is a 256Mb serial NOR flash memory, internally configured as 33,554,432 × 8 bits. In dual I/O or quad I/O mode, the organization changes to 134,217,728 bits × 2 or 67,108,864 bits × 4. The device uses an SPI and software protocol, operating on a simple 3-wire bus in single I/O mode. The three bus signals are clock input, serial data input, and serial data output. Serial access to the device is enabled via the CS# input. In dual I/O read mode, the SI and SO pins become SIO0 and SIO1 pins for address/dummy bit input and data output. In quad I/O read mode, the SI, SO, and WP# pins become SIO0, SIO1, and SIO2 pins for address/dummy bit input and data output. The HG25Q256B supports sequential read operations across the entire chip. After a program/erase command is issued, an automatic program/erase algorithm executes to program/erase and verify the specified page or sector/block location. Program commands can be executed by byte, page, or word. Erase commands can be executed by 4K-byte sector, 32K-byte block, 64K-byte block, or full chip. A status register is included for convenient user interfacing to indicate chip status. A status read command can be issued to check the completion status of program or erase operations via the WIP bit. Advanced security features enhance protection and security functionality. When the device is not in operation and CS# is high, it enters standby mode. The HG25Q256B uses a proprietary memory cell that reliably retains data even after 100,000 program and erase cycles.

Key features

• SPI support — Mode 0 and Mode 3
• Single supply operation: 2.7V to 3.6V for read, erase, and program operations
• Organization: 268,435,456 × 1-bit, or 134,217,728 × 2-bit, or 67,108,864 × 4-bit
• Protocol support: single I/O, dual I/O, and quad I/O
• Latch-up protection: 100mA from -1V to Vcc+1V
• Low Vcc write inhibit voltage: 1.5V to 2.5V
• SPI mode fast read: up to 133MHz clock frequency for all protocols
• Supports Fast Read, 2READ, DREAD, 4READ, QREAD instructions
• Supports double transfer rate mode
• Configurable dummy cycles for fast read operations
• Performance enhanced mode support — Execute-In-Place (XIP)
• Quad peripheral interface
• 4K-byte uniform sectors, or 32K-byte/64K-byte uniform blocks
• Individual block erase
• Programming: 256-byte page buffer; quad I/O page program for enhanced programming performance
• Typical 100,000 erase/program cycles
• 20-year data retention
• Input data format: 1-byte command code
• Advanced security features: block lock protection; individual sector protection
• Additional 4K-bit secure OTP memory: with identifier; factory-lockable identifiable, customer-lockable
• Software reset
• Program/erase suspend and resume operations
• Electronic identification: JEDEC 1-byte manufacturer ID and 2-byte device ID; RES instruction for 1-byte device ID; REMS instruction for 1-byte manufacturer ID and 1-byte device ID
• Serial Flash Discoverable Parameters (SFDP) mode support
• Serial clock input
• Serial data input, or serial data I/O for 2×I/O and 4×I/O read modes
• Serial data output, or serial data I/O for 2×I/O and 4×I/O read modes
• Hardware write protect, or serial data I/O for 4×I/O read mode
• Hardware reset pin, or serial data I/O for 4×I/O read mode
• Hardware reset pin
• No connect, or serial data I/O for 4×I/O read mode
• Package: 8-pin SOP; all devices are RoHS compliant and halogen-free