KSZ9031RNXIC-TR

The KSZ9031RNX is a completely integrated triple-speed (10BASE-T/100BASE-TX/1000BASE-T) Ethernet physicallayer transceiver for transmission and reception of data on standard CAT-5 unshielded twisted pair (UTP) cable. The KSZ9031RNX provides the Reduced Gigabit Media Independent Interface (RGMII) for direct connection to RGMII MACs in Gigabit Ethernet processors and switches for data transfer at 10/100/1000 Mbps. The KSZ9031RNX reduces board cost and simplifies board layout by using on-chip termination resistors for the four differential pairs and by integrating an LDO controller to drive a low-cost MOSFET to supply the 1.2V core. The KSZ9031RNX offers diagnostic features to facilitate system bring-up and debugging in production testing and in product deployment. Parametric NAND tree support enables fault detection between KSZ9031 I/Os and the board. The LinkMD TDR-based cable diagnostic identifies faulty copper cabling. Remote and local loopback functions verify analog and digital data paths. The standard KSZ9031RNX is available in a 48-pin, lead-free QFN package, and the AEC-Q100 automotive qualified parts, KSZ9031RNXUA/UB and KSZ9031RNXVA/VB, are available in a 48-pin lead-free VQFN (wettable) package.

Applications

• Laser/Network Printer
• Network Attached Storage (NAS)
• Network Server
• Gigabit LAN on Motherboard (GLOM)
• Broadband Gateway
• Gigabit SOHO/SMB Router
• IPTV
• IP Set-Top Box
• Game Console
• Triple-Play (Data, Voice, Video) Media Center
• Industrial Control
• Automotive In-Vehicle Networking

Key features

• Single-Chip 10/100/1000 Mbps Ethernet Transceiver Suitable for IEEE 802.3 Applications
• RGMII Timing Supports On-Chip Delay According to RGMII Version 2.0, with Programming Options for External Delay and Making Adjustments and Corrections to TX and RX Timing Paths
• RGMII with 3.3V/2.5V/1.8V Tolerant I/Os
• Auto-Negotiation to Automatically Select the Highest Link-Up Speed (10/100/1000 Mbps) and Duplex (Half/Full)
• On-Chip Termination Resistors for the Differential Pairs
• On-Chip LDO Controller to Support Single 3.3V Supply Operation – Requires Only One External FET to Generate 1.2V for the Core
• Jumbo Frame Support up to 16 KB
• 125 MHz Reference Clock Output
• Energy Detect Power-Down Mode for Reduced Power Consumption When the Cable is Not Attached
• Wake-On-LAN (WOL) Support with Robust Custom-Packet Detection
• Programmable LED Outputs for Link, Activity, and Speed
• Baseline Wander Correction
• LinkMD TDR-Based Cable Diagnostic to Identify Faulty Copper Cabling
• Parametric NAND Tree Support to Detect Faults Between Chip I/Os and Board
• Loopback Modes for Diagnostics
• Automatic MDI/MDI-X Crossover to Detect and Correct Pair Swap at all Speeds of Operation
• Automatic Detection and Correction of Pair Swaps, Pair Skew, and Pair Polarity
• MDC/MDIO Management Interface for PHY Register Configuration
• Interrupt Pin Option
• Power-Down and Power-Saving Modes
• Operating Voltages - Core (DVDDL, AVDDL, AVDDL_PLL): 1.2V (External FET or Regulator) - VDD I/O (DVDDH): 3.3V, 2.5V, or 1.8V - Transceiver (AVDDH): 3.3V or 2.5V (Commercial Temp.)
• AEC-Q100 Grade 3 (KSZ9031RNXUA/UB) and Grade 2 (KSZ9031RNXVA/VB) Qualified for Automotive Applications
• 48-pin QFN (7 mm×7 mm) Package