RS595SXS16

RS595S is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Separate clocks are provided for both the shift register and storage register. The shift register has an asynchronous reset (MR(overline)) input, serial (SER) input, and serial outputs (Q7S) for cascading. A low on MR(overline) will clear the shift register. Data is shifted on the LOW-to-HIGH transitions of the SRCLK input. The data in the shift register is transferred to the storage register on a LOW-to-HIGH transition of the RCLK input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. Data in the storage register appears at the output whenever the output enable input (OE(overline)) is Low. A High on OE(overline) causes the outputs to assume a high-impedance OFF-state. Operation of the OE(overline) input does not affect the state of the registers.

Applications

• Enterprise and communications
• Industrial
• Personal electronics
• LED displays Servers

Key features

• 8-bit serial input, parallel output shift
• Serial Output (Q7S)
• Power-Supply Range: 2V to 5.5V
• Low power consumption: 160μA(Max)
• Low input current: 1μA(Max)
• Shift register has direct clear
• Storage register with 3-state outputs
• Extended Temperature: -40°C to ±125°C