Varnitronics
SN74AHCT123ADR TI
TI

SN74AHCT123ADR

Schmitt trigger SOIC-16 Multivibrators RoHS

SOIC-16ROHS3 CompliantActive
Manufacturer
TI
Manufacturer part #
SN74AHCT123ADR
Store part #
C2863817
Package / case
SOIC-16
Packaging
Tape & Reel (TR)
Datasheet (PDF)

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100% Authentic · 30-Day Return or Replacement · policy

2,106 in stock

#C2863817

Stock & price checked 23 h ago

QuantityUnit pricePack price
1+₹71.12₹71.12
10+₹60.06₹600.60
30+₹52.47₹1,574.10
100+₹45.97₹4,597.00
500+₹44.02₹22,010.00
1,000+₹42.72₹42,720.00

1 × ₹71.12

₹71.12

excl. GST

₹83.92 incl. 18% GST

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  • GST invoice with every order
  • Standard pack: 2,500 per reel

SN74AHCT123ADR

₹71.12 for 1 + GST

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Specifications

Input Type
Schmitt trigger
Logic Type
Monostable
Number Of Channels
2

Packaging & compliance

RoHS
ROHS3 Compliant
Lifecycle
Active
Moisture sensitivity
MSL 1 (unlimited)
ECCN
EAR99
Packaging
Tape & Reel (TR)
Standard pack
2,500 / Reel
Sold per
Piece
Minimum order
1
Unit weight
0.2 g

Overview

The SNx4AHCT123A is a dual retriggerable monostable multivibrator. This device is an edge-triggered multivibrator with three methods available to control the output pulse duration. The output pulse duration can be programmed by selecting external resistor and capacitor values. The external timing capacitor must be connected between Cext and Rext/Cext (positive terminal), and the external resistor must be connected between Rext/Cext and VCC. For variable pulse duration, a variable external resistor can be connected between Rext/Cext and VCC. In addition, the output pulse duration can be shortened by driving CLR low. Pulse triggering occurs at specific voltage levels and is independent of the input pulse transition time. Schmitt-trigger inputs on A, B, and CLR provide sufficient hysteresis to accommodate slow input transition rates while ensuring glitch-free triggering at the output. After triggering, the basic pulse duration can be extended by retriggering via the active-low (A) or active-high (B) gating inputs. Driving CLR low terminates the pulse duration; the CLR input can be used to override inputs A or B. For given external timing components, output pulse duration variation between devices is typically less than ±0.5%. During power-up, the Q output is in the low state and the Q̄ output is in the high state. The outputs are glitch-free and no reset pulse is required.

Key features

  • TTL-compatible inputs
  • Schmitt-trigger circuits on A, B, and CLR inputs for slow input transition rates
  • Edge-triggered via active-high or active-low gating logic inputs
  • Retriggerable for very long output pulses
  • Output pulse terminable via override clear
  • Latch-up performance exceeds 100mA per JESD 78 Class II

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