SN74LS165ADR

The 165 and 'LS165A are 8-bit serial shift registers that shift data in the QA-to-QH direction on each clock pulse. Each storage element is accessible in parallel through eight individual direct data inputs, enabled by a low level on the shift/load (SH/LD) input. These registers also feature a gated clock (CLK) input and complementary outputs from the 8th bit. All inputs are diode-clamped to minimize transmission-line effects and simplify system design. The clock is implemented through a 2-input positive-NOR gate, allowing one input to serve as a clock inhibit function. Holding either clock input high inhibits the clock; when SH/LD is high and either clock input is held low, the other clock input is enabled. The clock inhibit (CLK INH) input may be changed to high only while CLK is high. Parallel loading is inhibited as long as SH/LD is high. When SH/LD is low, data on the parallel inputs is loaded directly into the register, independent of the CLK, CLK INH, or serial (SER) input levels. This device family is available in multiple package types: SN54165 and SN54LS165A are offered in J or W packages; SN74165 in the N package; SN74LS165A in D, N, or NS packages; SN54LS165A is also available in the FK package, with some pins having no internal connections.

Key features

• Complementary outputs
• Direct overriding (data) input
• Gated clock input
• Parallel-to-serial data conversion