SN74LVC1G10DCKR

Available in the NanoFree™ Package Supports 5-V Vcc Operation Inputs Accept Voltages to 5.5 V Provides Down Translation to Vcc Max tpd of 3.8 ns at 3.3 V Low Power Consumption, 10 μA Max ICC ±24 mA Output Drive at 3.3 V Ioff Supports Live Insertion, Partial-Power Down Mode, and Back Drive Protection Latch-Up Performance Exceeds 100 mA per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged Device Model (C101) The SN74LVC1G10 performs the Boolean function Y = A·B·C(overline) or Y = A(overline)+B(overline)+C(overline) in positive logic. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

Key features

• Available in NanoFree package
• 5V VCC operation supported
• Inputs tolerant up to 5.5V
• Down-translation to VCC voltage supported
• Maximum propagation delay tpd of 3.8ns at 3.3V
• Low power consumption, maximum quiescent current Icc of 10μA
• Output drive capability of ±24mA at 3.3V
• Ioff supports hot insertion, partial power-down mode, and back-drive protection
• Latch-up performance exceeds 100mA, compliant with JESD 78 Class II
• ESD protection compliant with JESD 22: 2000V Human Body Model, 200V Machine Model, 1000V Charged Device Model
• All unused inputs must be tied to VCC or GND to ensure proper device operation
• Built-in ESD protection is limited; during storage or handling, short the pins together or place the device in conductive foam to prevent electrostatic damage to MOS gates